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Azuro has announced Rubix, a clock concurrent optimisation tool.

Rubix combines the separate design flow steps of physical optimisation and clock tree synthesis (CTS) to deliver up to 20 per cent increases in chip speed and reduce time to market.

Physical optimisation is the step in the design flow that most influences chip speed, area and power.

But physical optimisation occurs before clocks are inserted into a design during the clock tree synthesis step and makes decisions based on an idealised, balanced model of clocks.

At 65nm and below, this model has diverged from reality due to three key industry trends: design complexity, on-chip variation and low power.

This divergence directly impacts the validity of decisions made during physical optimisation, degrading achievable chip speed and causing a spike in manual iterations in design flows.

Clock concurrent optimisation addresses this divergence by building clocks during – rather than after – physical optimisation and therefore makes all decisions based on real clocks, not idealised clocks.

Using an idealised, balanced model of clocking, the time available for logic functions between registers is assumed to be equal, and chip speed is therefore limited by whichever logic function on a chip is slowest.

Since clock concurrent optimisation builds clocks simultaneously with optimising logic, the time available for logic functions need not be the same and can be varied by individually controlling when clock signals arrive at registers.

Using clock concurrent optimisation, chip speed becomes limited by whichever ‘chain’ of logic functions is slowest, where these chains break only when they reach an input to, or an output from, a chip or when they loop back on themselves.

It is the explicit minimisation of critical logic chains, as opposed to critical logic paths, which most differentiates clock concurrent optimisation from traditional physical optimisation.

‘Neither the RTL coding languages used to design chips nor the verification tools used to sign off on final chip layouts requires that clocks be balanced,’ said Steve Teig, former chief technical officer of Cadence Design Systems.

‘Since idealised clocks no longer match reality, giving up on the idea of balancing is a win-win situation; timing optimisation can be based on real clocks, and the lack of any requirement to balance clocks offers new freedoms to increase chip speed,’ he added.

Rubix uses the same flow integration interface used by Powercentric, Azuro’s CTS solution.

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