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Silicon Laboratories has introduced the SI5374 and SI5375 integrated clock ICs, designed to address the complex timing requirements of high-speed optical transport network (OTN) applications.

Utilising the company’s DSPLL technology, the SI5374 and SI5375 clocks are single-chip timing ICs that integrate four independent, high-performance phase-locked loops (PLLs), providing twice the PLL integration and 40 per cent lower jitter than competing solutions.

OTN is a next-generation protocol (ITU G.8251 and G.709) that provides an efficient way to multiplex different services onto optical networks, making it suitable for edge routers, wavelength division multiplexing (WDM) transmission equipment, Carrier Ethernet and multi-service platforms.

Silicon Laboratories said OTN applications pose complex timing challenges by requiring low-jitter clocks at non-integer-related frequencies.

The company’s quad-DSPLL SI537x devices produce up to eight low-jitter output clocks, simplifying the design of any-protocol, any-port 10G, 40G and 100G OTN line cards.

Each DSPLL clock multiplier can be configured to generate any frequency from 2kHz to 808MHz from a 2kHz to 710MHz input.

This frequency flexibility reduces the cost and complexity of multi-protocol OTN line cards by minimising the need for multiple jitter-cleaning clock ICs.

The SI537x devices’ flexible DSPLL architecture simplifies the generation of high-speed PHY reference clocks with jitter performance of 0.4 picoseconds, eliminating the need for discrete VCXO-based PLLs currently used in OTU3 and OTU4 applications.

The SI537x devices can reliably lock to gapped clock inputs – a critical OTN line card clock requirement – without separate upstream low-bandwidth PLLs.

Other carrier-grade features include SONET-compatible jitter peaking (0.1dB maximum) and a hitless switching capability that minimises output clock phase transients during reference switching, producing a 25 times smaller phase transient than competing solutions, according to Silicon Laboratories.

Each DSPLL engine features a fully integrated loop filter that supports user-programmable bandwidths as low as 4Hz, enabling wander filtering in addition to jitter attenuation, configurable on a per-channel basis.

The SI5374 device has eight input clocks and eight output clocks, while the SI5375 offers four input clocks and four output clocks for applications requiring fewer clocks.

With its quad-DSPLL configuration, a single SI5374 clock can generate different frequencies simultaneously, enabling the design to support SONET/SDH, 1/10/100G Ethernet, 1/2/4/8/10G Fibre Channel, 3G/HD SDI video and other protocols simultaneously in the same device.

The SI537x clocks provide a smooth upgrade path for existing customers migrating from Silicon Laboratories’ SI5319/26 jitter-attenuating clocks to a more integrated jitter-cleaning clock solution designed to minimise bill-of-material cost and complexity.

The clocks effectively replace four timing devices with a single IC in high-port-count 10G/40G/100G OTN line cards.

SI537x clock prices range from USD39 (GBP24) to USD59 in 10,000-unit quantities.

The SI5374-EVB and SI5375-EVB evaluation kits are available for USD350 each.

Silicon Laboratories

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