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Apache Design Solutions has released CPM v2.0, its next-generation Chip Power Model (CPM) intended for true co-analysis/co-optimisation of the chip, package and system.

Suitable for wireless and automotive markets, including 3D IC and SiP designs, the release of CPM v2.0 expands the range of coverage to include system resonance awareness, the power-transition impact on a global power delivery network (PDN), thermal co-analysis, and EMI and EMC validation.

It also delivers user configurable models for an effective CPS flow.

Apache’s resonance-aware CPM v2.0 model considers the LC resonance frequency of the system and automatically generates an on-die switching scenario operating at or near the system resonance.

This enables system designers to access a CPM representing the worst case switching scenario that can be used for stress testing the CPS design.

By using resonance-aware models, designers can determine the optimal placement and configuration of the package and PCB decoupling capacitance to help manage power and noise.

CPM v2.0 models on-die power transient waveform over a long duration to capture the envelope modulating the high-frequency switching.

This represents middle- to low-frequency components on the chips, which impacts the global PDN and needs to be handled by package and PCB power-supply system.

The power-transition model allows system designers to simulate load-step conditions to identify and debug weaknesses in their package and system designs.

In 3D-IC and SiP designs, thermal integrity becomes a major challenge for chip-package-system co-design.

The power mapping in CPM v2.0 enables package designers to accurately predict the thermal distribution and hot spots of multiple die in a stacked die packaging.

In automotive and wireless markets, using on-chip LDO voltage regulators is increasing, but a key design concern is EMI and EMC.

The expanded capability of CPM v2.0 delivers a power model that contains the LDO circuitry that is critical to system-level EMI and EMC validation.

Apache’s CPM v2.0 offers enhanced usability with user-configurable models for system-level ‘what-if’ analysis of various IC switching scenarios.

Chip designers can create multiple current profiles for various blocks within the design, enabling system designers to simulate power-switching scenarios and exhaustively verify their system.

In addition, CPM v2.0 adds probing of internal nodes for interactive dynamic power analysis.

This provides system designers with access to the critical areas of chip for enhanced debugging and optimisation.

System designers can explore the addition of decoupling capacitance at a high power node of the IC to reduce the dynamic voltage drop, instead of adding them onto the package, which can result in higher costs.

This flexibility allows system designers to make educated co-optimisation decisions without an iterative loop of requesting an updated model from IC designers.

CPM is a compact and Spice-accurate model of the full-chip power-delivery network.

It contains spatial and temporal switching current profiles, as well as parasitics of non-linear on-chip devices including decaps, loading capacitance and power/ground coupling capacitance.

CPM represents the entire die power delivery network with ports at the die level C4 bumps and/or pads.

It accurately models the electrical response of the chip for a range of frequency, from DC to multi-GHz, enabling the analysis, diagnostics and optimisation of system-level power integrity designs.

For existing Apache Redhawk-CPM customers, CPM v2.0 is available as a no-cost upgrade.

Apache Design Solutions

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