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Mentor Graphics has announced the new Calibre Realtime platform for signoff-quality physical verification during design creation, improving design speed and quality of results.

The first release provides instantaneous design rule checking (DRC) in the Springsoft Laker custom-IC design and layout software, using the same Calibre decks as the signoff flow.

The software improves design speed and quality of results by giving designers, for the first time, the full power of Calibre’s signoff engines and qualified checks during design.

This allows them to optimise their layouts for performance without sacrificing manufacturing yield.

A version for the Mentor IC Station custom-design environment will be available in June.

According to the company, the flow is seamless and virtually instantaneous, allowing designers to use foundry-qualified verification information during design optimisation in real time.

Because the implementation fits naturally into the design flow, the learning curve is fast.

Having the signoff design rule checks in real time, while creating the layout, allows the designer to break the LVS-DRC-LVS loop.

When a block is LVS-clean, it’s DRC-clean and ready for extraction.

The platform thus changes the layout-verification-simulation flow and lets designers focus on getting the best results possible.

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