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Tensilica has extended its Baseband Engine (BBE) range with the Connx BBE64-128 – the next-generation architecture for DSP IP cores for SOC (system-on-chip) design.

The Connx BBE64-128 provides over 100 GigaMACs performance in 28nm high-performance process technology.

The Connx BBE64-128 was designed to meet the performance requirements for LTE (Long-Term Evolution) Advanced, which required at least five times more processing power than LTE.

Additionally, Tensilica introduced the Connx BBE64-UE, which is specifically optimised for the low-power and small-area requirements of LTE advanced handsets.

These two products are based on the Connx BBE64 architecture, which Tensilica’s customers can use to optimise a DSP core for their particular requirements.

Tensilica’s product line also includes DSPs for LTE, including the Connx BBE16 LTE DSP and the new Connx SSP16, Connx BSP3 and Connx Turbo16.

The Connx BBE64-128 DSP can perform at 128 MACs per cycle for maximum throughput and minimum energy for most common MIMO (multiple in, multiple out) and channel-estimation functions, used extensively in LTE Advanced software.

It is based on a multislot VLIW (very long instruction word) architecture that provides high sustained performance across many applications with dense code and power efficiency.

For non-vector algorithms, high code density can be achieved with modeless switching to Tensilica’s smaller standard 16- and 24-bit instructions.

Almost any operation can be performed from any slot in the VLIW format for greater sustained performance, lower energy and denser code.

This flexibility allowed Tensilica to design the BBE64-128 so it can run 128 MACs (multiply accumulates), which is particularly helpful for FIR (finite impulse response) filters and matrix operations that dominate LTE Advanced channel estimation and MIMO processing.

Other features of the Connx BBE64-128 that accelerate performance include: high-performance ‘soft bit’ vector data types and operations, including arbitrary field insertion and extraction for complex transmit operations, resulting in over 250 general 10-bit operations per cycle; parallel register files for 10/20-bit and 40-bit data types for easier compilation and higher performance at lower power; large register files for performance on complex code, reduced memory bandwidth requirements, reduced power and easier compilation; single-cycle 16-way complex radix-4 and radix-8 FFT (fast Fourier transform) and DFT (discrete Fourier transform) for efficiency on arbitrary size transformations common to OFDM (orthogonal frequency-division multiplexing) algorithms; accelerated interleaving for all bit, byte, half-word and word vector types for flexibility and efficiency in HARQ (hybrid automatic repeat request), forward error correction and convolutional coding; cellular modem acceleration with an optimised capability for max-index search, demap, despread, vector divide, vector recip and square root – rich operation resources – multiple parallel execution units of each type to provide greater instruction scheduling flexibility and higher performance on code that uses one execution type heavily; expanded vector memory operations for easier automatic compilation of complex C code at maximum performance on any data size and placement; a high-performance AXI interface for easy shared memory connection to memory and other cores; extensibility – the ability to optimise design for specific needs by adding custom instructions in minutes with Tensilica’s automated tools – allows great design flexibility for adding special memory interfaces, special per-SIMD (single instruction, multiple data) lane lookups or other required functions; the widest range of pre-defined ‘point-and-click’ configuration options in Tensilica’s history for maximum design flexibility; handsets and other user equipment have extremely tight power budgets, as well as restrictions on the total area of the design; Connx BBE64-UE was developed with this in mind and is based on a minimum feature set for minimum energy and latency.

It is optimised for interface with low-power specialised engines (programmable or hard wired).

While excluding such features as the option to run 128 MACs/cycle, this high-efficiency processor can reach approximately 300,000 GMAC/second/Watt in 28nm low-leakage process technology.

Because the Connx BBE64 family is based on Tensilica’s patented customisable processor technology, various functions can be tailored, turned on or off and added to during the SOC design process.

All hardware changes are quickly reflected in the automatically generated compiler and complete software tool chain exactly matching all configuration options and additional instruction extensions.

The compiler is automatically generated to match the exact configuration options chosen during the design process and features full native DSP data-type support (integer/fractional, real/complex).

It automatically infers complex instructions, accelerates and vectorises legacy code from Connx BBE16, accelerates legacy code written with industry-standard intrinsic functions, vectorises loops with complex conditional operations and performs ANSI C operators on vector datatypes.

It comes with improved tools and an ‘analysis cockpit’ for program analysis, including a vectorisation assistant.

A complete evaluation kit for the Connx BBE64-128 and Connx BBE-UE cores is expected to be available for early-access customers in the autumn of 2011.

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