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Faraday Technology has announced the availability of its MiniIO IO pads at 55nm and 65nm.

Compared with general IO pads, the MiniIO reduces the chip area by up to 40 per cent for a pad-limited design with 500 pins, while keeping the same programming IO functionality and achieving robust ESD performance.

Targeted for fabless design houses in multi-voltage applications (1.8V-3.3V), the MiniIO has been silicon proven via complete functional verification.

The ultra-fine pitch of Faraday’s 55nm/ 65nm MiniIO surpasses the average pad pitch rules (25um pad pitch in 2 row staggered).

The MiniIO supports Tri-Tier Bonding and BOAC with a fine bonding pitch of 16-17um, meeting demand for high-pin counts.

In addition, Faraday’s 55nm/65nm MiniIO provides slimmer power pads, input I/O buffers and output/bi-di I/O buffers with widths of 17nm.

They can support BOAC.

Faraday Technology

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