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Faraday Technology has announced the availability of its commercial USB 3.0 physical layer (PHY) at UMC 90nm high-speed (HS) process.

Said to have a smaller size and lower power consumption than its peers, the component is developed based upon USB 3.0 version 1.0 specification functionally and electrically, achieving the maximum speed of 5.0Gbps.

To achieve the target of low-power design in 90nm, Faraday has carried out improvement in the PHY architecture, including a regulated PLL structure to reduce design corners.

Faraday introduced a dual-loop half-rate structure for CDR and adopted the active peaking method to increase the effective bandwidth for transmitter to meet 5Gbps data rate with lower current consumption.

The USB 3.0 PHY in UMC 90nm will be shown at USB Devcon on 1-2 April in Taipei.

Faraday Technology

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