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Altera Corporation has announced two FPGA ranges with integrated transceivers.

The Arria II GX, Stratix IV GT, and Stratix IV GX FPGAs and Hardcopy IV GX ASICs utilise common transceiver technology and are supported by a set of development tools that enable system designers to develop full system-on-chip (SoC) solutions.

This portfolio delivers both FPGA solutions from 16K logic elements (LEs) to 530K LEs, and Hardcopy ASIC solutions of up to 11.5 million ASIC gates.

The programmable fabric and integrated programmable transceivers provide designers with the flexibility needed to overcome unpredictable design requirements.

Altera said its transceiver technology provides signal integrity features that accelerate product development, while consuming less power than competing solutions.

The high-performing FPGAs, Stratix IV GT devices, include integrated transceivers operating at 11.3Gbps.

The architecture is optimised specifically for 40G and 100G applications such as communications systems, high-end test equipment, and military communications systems.

Stratix IV GT FPGAs have 24 transceivers operating at 11.3Gbps, and an additional 24 transceivers operating at 6.5Gbps.

The Stratix IV GT devices also offer up to 530K LEs, 20.3Mbits internal RAM and 1,288 18 x 18 multipliers.

Arria II GX devices are the low-power 3.75Gbps transceiver FPGAs and are optimised for applications using mainstream protocols such as PCI Express (PCIe) and Gigabit Ethernet (GbE).

They feature up to 16 3.75Gbps transceivers, 256K LEs, and 8.5Mbits of internal RAM.

The Arria II GX FPGAs also support targeted protocols such as CPRI for LTE and WiMAX wireless infrastructure access equipment; GPON and XAUI for wireline infrastructure access and networking equipment; and triple-speed SDI for broadcast and other video processing equipment.

A collection of reference designs and design examples accelerates the development of solutions using Arria II GX FPGAs.

The FPGAs and Hardcopy ASICs are supported by Altera’s Quartus II design software version 9.0.

The design software provides a single tool suite for all FPGA and ASIC products, complemented by one IP set and a common transceiver technology.

Together, this delivers the ‘learn it once, use it everywhere’ experience that can increase system designer productivity while reducing time to market and expenses.

Altera also provides a suite of tools to ease transceiver integration and board design, including the pre-emphasis and link estimation (PELE) tool, the power distribution network (PDN) tool, and the early simultaneous switching noise (SSN) estimator.

Hardcopy IV GX ASICs are the lowest risk ASICs with transceivers.

Designers can prototype with the Stratix IV GX FPGA series and migrate to Hardcopy IV GX ASICs to achieve low total cost, low risk and fast time to market.

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