Product Details Supplier Info More products

Fujitsu Microelectronics Europe has announced the availability of its Charge-mode Interleaved Sampler (CHAIS) technology for use in its standard 65nm CMOS process technology.

The ADC technology provides performance levels in a standard CMOS process, enabling the integration of multiple ADCs with tens of millions of gates of signal processing logic and memory on a single chip.

Initially targeting use in coherent receivers for 100G optical transmission, the technology is also applicable to high-end test equipment and any other system requiring high-speed data conversion and processing.

The CHAIS circuits avoid many of the limiting factors, such as restricted bandwidth and poor linearity, of conventional architectures to make ADCs with sampling rates of up to 100GSa/s feasible in CMOS.

Power consumption for the ADC is 2W typical per channel at 56GSa/s.

A 1.75GHz input reference clock is internally multiplied to provide ADC sampling clocks with less than 100fs total rms jitter and less than 500fs I/Q ADC skew.

The first production application of this ADC technology will be a single-chip DP-DQPSK coherent receiver for 100G optical networks, with four-channels of 56GSa/s 8-bit ADCs (I and Q signals, H and V polarisation) integrated with logic and memory to perform the complete receive PHY function when connected directly to the optical front-end.

A single-chip solution avoids the need to transfer terabits-per-second of data between ADC and DSP chips – reducing power consumption, silicon area and number of I/O pins.

The need for multi-chip module (MCM) technology is eliminated.

The increased ADC resolution and sampler dynamic range eases the design of the optical front-end by allowing part or all of the AGC function to be realised digitally after the ADC.

Continuous digital background self-calibration during operation means that external calibration test signals or non-volatile calibration memory are not required, and no user intervention is needed to achieve and maintain the specified performance levels.

The ADC will initially be available in 2009 in Fujitsu’s CS200 65nm process technology as two-channel and four-channel 56GSa/s 8-bit macro cells.

Other channel counts, sampling rates, resolutions and process nodes will follow according to market demands.

Fujitsu Semiconductor

View full profile