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Lattice Semiconductor and Affarii Technologies have announced that they have developed a complete 3G/4G-based Remote Radio Head (RRH) solution for wireless infrastructure customers.

The solution includes Digital Up/Down Converter (DUC/DDC), Crest Factor Reduction (CFR) and Digital Pre-Distortion (DPD) functionality.

Lattice provides CPRI/OBSAI and Ethernet technology implemented on the ECP3 FPGA’s low-cost 3G SERDES transceivers.

A fully integrated RRH solution is available, providing baseband processing for up to two transmit and four receive antennas on a single silicon device, with each antenna supporting four carriers and 20MHz of modulation bandwidth.

When used with industry-standard Doherty amplifiers, the Digital Predistortion provides up to 30dB of ACLR correction per transmit antenna, with PA output efficiencies exceeding 40 per cent.

The solution is fully customisable, with end applications including WCDMA, LTE, WiMAX, WiBro, TD-SCDMA and DVB-T/S/H.

The RRH solution is supported by a development and test environment that includes GUI-based design simulation, performance analysis and a production test API with design examples.

An in-circuit hardware development platform is also being developed.

The mid-range LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3G SERDES, DDR1/2/3 memory interfaces and high performance, cascadable DSP slices that are suitable for high-performance RF, baseband and image-signal processing.

Toggling at 1Gbps, the LatticeECP3 FPGAs are also said to feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8Mb.

Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O.

The LatticeECP3 FPGA family’s high-performance features include: 3.2Gbps SERDES with the ability to mix and match multiple protocols including CPRI, OBSAI, XAUI, Serial RapidIO, PCI Express, 10GbE and SGMII/Gigabit Ethernet on each SERDES quad.

The SERDES/PCS blocks have been designed to enable the design of the low-latency variation CPRI links that are found in wireless basestations with Remote Radio Head connectivity.

DSP blocks allowing up to 36 x 36 multiply and accumulate functions running at more than 400MHz.

The DSP slices also feature cascadability for implementing wide ALU and adder tree functions without the performance bottlenecks of FPGA logic.

1Gbps LVDS I/O with Input Delay blocks allows interfacing to high-performance ADCs and DACs.

With these features, the LatticeECP3 FPGA solution is suited for high-volume, cost- and power-sensitive wireless RRH infrastructure equipment.

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