Product Details Supplier Info More products

Lattice Semiconductor Corporation has announced the availability of samples of the Lattice ECP3-150 FPGA.

The ECP3-150 features a DSP capacity of 320 18×18 multipliers, 6.8Mb of memory and up to sixteen 3.2Gb/ps Serdes channels, making it suited to complex, integrated Wireless Remote Radio Heads (RRH) such as Mimo-based RF antenna solutions.

The ECP3-150 FPGA also provides Wireline Access developers with high-density, low-cost, low-power Ethernet, Sonet and PCI Express solutions.

The Lattice ECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3G Serdes, DDR1/2/3 memory interfaces for low-cost FPGAs and cascadable DSP slices that are suitable for high-performance RF, baseband and image-signal processing.

Toggling at 1Gb, the Lattice ECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8Mb, according to the company.

Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O.

The LatticeECP3 FPGA family’s features include: 3.2Gb/ps Serdes with 10Gb E XAUI jitter compliance and the ability to mix and match multiple protocols on each Serdes quad.

This includes PCI Express, CPRI, OBSAI, XAUI, Serial RapidIO and SGMII/GbE.

The Serdes/PCS blocks have been designed to enable the design of the low latency variation CPRI links that are found in wireless basestations with Remote Radio Head connectivity.

They are Compliant with the SMPTE Serial Digital Interface standard and have the ability to support 3G, HD and SD video broadcast signals independently on each Serdes channel.

The triple-rate support is performed without any oversampling technique, consuming the least possible amount of power.

DSP blocks allow up to 36×36 Multiply and Accumulate functions running at more than 400MHz.

The DSP slices also feature cascadability for implementing wide ALU and adder-tree functions without the performance bottlenecks of FPGA logic.

1Gb/ps LVDS I/O, with Input Delay blocks, allows interfacing to high performance ADCs and DACs.

With these features, the LatticeECP3 FPGA family is suited to high-volume cost- and power-sensitive wireless infrastructure and wireline access equipment, as well as video and imaging applications.

The LatticeECP3 FPGA family is supported by the Isplever design tool suite, version 7.2 Service Pack two.

It provides a complete set of tools for all design tasks, including project management, IP integration, design planning, power analysis, place and route and on-chip logic analysis.

The Isplever tool suite is provided on CD-ROM and DVD for Windows, UNIX or Linux platforms.

Synopsys’ Synplify Pro advanced FPGA synthesis is included for all operating systems supported, and Aldec’s Active-HDL Lattice Edition simulator is included for Windows.

Lattice devices are also supported by Mentor Graphics ModelSim SE and Precision RTL synthesis and the full versions of Synopsys Synplify Pro and Aldec Active-HDL.

View full profile