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Lattice Semiconductor has launched Version 1.0 of its Lattice Diamond field-programmable gate-array (FPGA) design software, enabling designers to target low-power, cost-sensitive FPGA applications.

This new flagship design environment for Lattice FPGA products provides a complete set of tools, design flows and a modern user interface.

‘We have used Lattice Diamond design software at Helion for the development of the Ionos line of video image processing pipeline IP and were very impressed by the level of integration of so many different and powerful software tools into one GUI [graphical user interface],’ said Dr Arndt Bussman, chief technical officer of Helion.

Mike Kendrick, Lattice’s manager of software product planning, added: ‘Diamond software gives our customers an easy-to-use, intuitive design environment that specifically addresses the critical design issues of cost-sensitive, lower-power applications.

‘As designs become larger and FPGAs are increasingly being used in more cost-sensitive, high-volume applications, designers need an easy-to-learn, flexible design environment for exploring different implementations to achieve their cost, power and performance targets.

‘The Diamond software allows designers to efficiently manage these multiple implementations in one project,’ he said.

Kendrick added that the software provides the same features found within the Isplever design environment that are specifically developed for low-cost and low-power applications.

‘These include a very accurate power calculator, a simultaneous switching output noise calculator and the proven MAP and PAR FPGA implementation algorithms that take novel approaches to avoid congestion when targeting Lattice’s industry-leading FPGA product line,’ he said.

Diamond software enables designers to move quickly to the task at hand because navigation is direct.

Designers can manage their design view windows through the attach/detach feature.

This feature enables the activation of many alternate concurrent design views across the available screen space, while avoiding the clutter that could result without advanced window management.

Combined with the extensive cross probing between Diamond views, designers can quickly investigate their design implementation’s utilisation and critical timing.

Diamond software supports multiple design ‘implementations’.

The design source can be shared among implementations, or each implementation can have its own unique design source.

This allows design exploration from within the Diamond software; different approaches can be tried to evaluate their effect on design size, cost, performance and power.

Optimisation options for logic synthesis and place and route are captured as a ‘strategy’ that can be applied to any of the implementations.

Diamond software comes with a library of predefined strategies and users can also create their own and add them to this library.

A single strategy’s settings can be updated, for example to an alternate PAR algorithm tuned for highly connected designs, and run against several unique implementations to determine if the results better meet the design goals for cost, power and performance.

Finally, the Run Manager can launch a user-selected set of implementations to be run through the flow, exploiting multi-core processors, if available, to improve the elapsed time to final results.

The Diamond design environment includes many other design flow improvements that specifically improve designer productivity, particularly when targeting low-power, cost-sensitive applications.

For example, built-in HDL visualisation and code checking saves time by quickly catching coding errors and improving design documentation.

As another example, designers can quickly find, investigate and address timing issues using the new Timing Analysis View.

The Timing Analysis View facilitates the navigation of the static timing results.

When timing constraints are revised, direct updates to timing analysis avoid the potentially significant time required to re-implement the design.

Diamond software also includes extensive capabilities for scripting the design flow.

Tcl command dictionaries specific to the Diamond design environment are available for projects, netlists, HDL code checking, power calculation and hardware debug insertion and analysis.

The Diamond design environment is supported on Windows and Linux.

It includes support for Windows 7 and, under Windows 7 64 bit, Diamond software has access to a full 4G memory space.

This gives designers targeting large LatticeECP3 devices excellent system performance and flexibility, according to the company.

The Diamond design environment includes support for Windows XP, Windows Vista (32 bit) and Windows 7 (32 bit and 64 bit), as well as Linux (Red Hat Enterprise Linux and Novell SUSE).

Other Lattice design tools are available for download separately, including the Latticemico32 System and Isplever Classic, as well as the PAC Designer tools that target programmable mixed-signal design.

A Lattice Diamond licence will also enable any of those tools that are under licence control.

Synopsys’s Synplify Pro advanced FPGA synthesis is included for all operating systems supported, while Aldec’s Active-HDL Lattice Edition II simulator is included for Windows.

In addition to the tool support for Lattice devices provided by the OEM versions of Synplify Pro and Active-HDL, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL.

Mentor Graphics Modelsim SE and Precision RTL synthesis also support the latest Lattice devices, such as the LatticeECP3 FPGA range.

Lattice will continue to support its Isplever tool suite for FPGA design over the next 18 months, while transitioning its FPGA customer base to the Diamond design environment.

There are no changes to the Isplever Classic product, which targets CPLD and legacy FPGA devices.

The Lattice Diamond software is available now for download from the Lattice website for both Windows and Linux.

Once downloaded and installed, it can be used with either the Diamond free licence or the Diamond subscription licence.

The Diamond free licence can be immediately generated upon request from the Lattice website and provides access to many Lattice devices, such as the MachXO PLD range, the LatticeXP2 FPGA range and the LatticeECP2 FPGA range at no cost.

The Diamond free licence also enables Synopsys Synplify Pro for Lattice synthesis and Aldec Lattice Web Edition II simulation software.

The Diamond subscription licence that can be purchased adds support for all Lattice FPGAs, including the latest LatticeECP3 devices.

It enables Synopsys Synplify Pro for Lattice synthesis and the Aldec Lattice Edition II mixed language simulator for increased capacity and performance.

The Diamond subscription licence enables both the new Diamond software and the existing Isplever software from a single licence.

The Diamond subscription licence is priced at USD895 (GBP594) per year.

All Lattice Isplever software users under active maintenance agreements will receive a Diamond subscription licence at no charge that will expire one year from the Lattice Diamond 1.0 release date.

Lattice Semiconductor

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