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Lattice Semiconductor has announced Version 8.0 of its ISPLever FPGA design tool suite.

This latest version includes enhancements for the design of high-speed double data rate (DDR) interfaces for the LatticeECP3 FPGA range.

These enhancements include automatic interface code generation to increase design productivity and reduce coding errors, as well as enhanced timing analysis that provides more transparency to circuit timing details.

The IPexpress tool now can generate the HDL for the most appropriate generic DDR interface based on user requirements such as direction, speed and bus width.

This HDL has been specifically designed and validated for high-performance, robust operation.

For the ECP3 range, certain DDR interfaces can now be implemented with higher pin layout flexibility.

Since an important part of robust DDR interface operation is a clean transfer between the IO and fabric clock domains, the Trace static timing analysis report has been enhanced to include a Timing Rule Check section that specifically analyses these clock domain transfers.

This is done automatically and does not require users to define additional timing constraints.

The IPexpress tool can now also optionally generate the complete I/O-specific circuitry for proprietary DDR memory interfaces, allowing designers to focus solely on the controller logic of their DDR1 and DDR2 DRAM interfaces.

ISPLever 8.0 software is able to complete large, congested designs 30 per cent faster than with the previous ISPLever 7.2 SP2 release.

Lattice continues to enhance and expand support for the open source 32-bit RISC Latticemico32 ecosystem.

The GNU compiler (GCC) has been upgraded to Version 4.3.0, which enables higher system performance and more flexible code deployment options.

The Tri-speed MAC IP can now be interconnected to higher throughput configurations.

The component library includes a dual-port on-chip memory to enable high-speed information passing between Wishbone bus masters, while an enhanced SPI Flash controller allows both read and write access.

The ISPLever design tool suite provides a complete set of tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis and more.

Version 8.0 of the ISPLever software adds support for Red Hat Enterprise Linux 5.3.

Synopsys’ Synplify Pro advanced FPGA synthesis is included for all operating systems supported and Aldec’s Active-HDL Lattice Edition simulator is included for Windows.

The ISPLever 8.0 software also comes bundled with the Latticemico32 system and ISPLever Classic, as well as with the PAC Designer tools that target mixed signal design.

The ISPLever tool suite is provided on DVD for Windows, Unix or Linux platforms.

In addition to the tool support for Lattice devices provided by the OEM versions of Synplify Pro and Active-HDL, which are included in the ISPLever tool suite, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL.

Mentor Graphics Modelsim SE and Precision RTL synthesis also support the latest Lattice devices, such as the LatticeECP3 range.

The ISPLever 8.0 tool suite for Windows, Linux and Unix users is available immediately without charge for customers with active design tool maintenance contracts.

Lattice Semiconductor

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