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Lattice Semiconductor has released version 1.4 of its IspLever Classic design tool suite to provide a design environment for Lattice complex programmable logic devices (CPLD).

IspLever Classic has been upgraded with the addition of Synopsys Synplify Pro with the HDL Analyst feature set, and an improved IspMach 4000ZE CPLD fitter with improved power optimisation.

Synplify Pro HDL Analyst enables designers to rapidly visualise high-level register transfer level (RTL) Verilog or VHDL.

Designers can cross-probe between the graphical diagrams and source code to ensure that the coding style they use is the most efficient for the target CPLD.

Finite state machines (FSM), for example, are popular functions designed into CPLDs.

FSMs are automatically extracted by HDL Analyst and displayed graphically as a bubble diagram with state transition arrows and a table of state encodings.

To minimise the dynamic power consumption of IspMach 4000ZE CPLDs, the Classic 1.4 fitter now automatically enables the device’s Power Guard feature for unused I/O and clock resources to avoid unnecessary internal switching.

The IspLever Classic 1.4 software also includes improved features and educational material for the IspMach 4000 CPLD family.

The synthesis interface to the 4000 family has been upgraded with additional optimisation control and a means to reference a Synplify Design Constraints (SDC) file for timing objectives.

The IspLever Classic software Online Help has been expanded to make designing with Lattice CPLDs easier and more efficient.

Online Help now includes links to key technical ‘How To’ topics for IspMach 4000 architectural features and power estimation.

A ‘generic’ schematic library manual describes logic symbols that are portable across SPLD and CPLD device families.

The Classic 1.4 design software is bundled with the IspVM system 17.8 programming environment.

Designers can download IspLever Classic for Windows for free from Lattice’s website, as well as the optional Synopsys Synplify Pro logic synthesis and Aldec Active HDL simulator modules.

IspLever Classic is the design environment for Lattice CPLDs and mature programmable products.

It can be used to take a Lattice device completely through the design process, from concept to device JEDEC or bitstream programming file output.

The IspLever Classic for Windows tool suite is a free download from the Lattice website.

Lattice customers can access the latest PLDs and FPGAs, including the MachXO PLD family, from the Lattice Diamond design software.

Schematic/VHDL or Schematic/Verilog HDL Design Entry type projects created by IspLever Classic are forward-compatible with the Lattice Diamond design software.

In addition to the tool support for Lattice devices provided by the downloadable versions of Synopsys Synplify Pro for Lattice and Active-HDL Lattice Web Edition, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL.

The IspLever Classic 1.4 tool suite for Windows is available immediately for free.

Classic 1.4 software is compatible with Windows XP/Vista/7 and operates as a 32-bit application.

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