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Actel has brought out the Libero Integrated Design Environment (IDE) version 8.5, which extends support for the nano versions of Igloo and ProASIC3 field programmable gate arrays (FPGAs).

Libero IDE version 8.5 also introduces support for instantiation and configuration of embedded mathblocks for use in Actel’s radiation-tolerant RTAX-DSP family.

Actel nano FPGAs provide designers with an efficient method of developing portable systems based on the lowest power and smallest footprint FPGAs.

Libero IDE 8.5 adds design support for 16 distinct Igloo nano FPGAs in six different package types and six distinct ProASIC3 nano FPGAs in three different packages.

Actel nano FPGAs range from 10 to 250k system gates, with select package offerings of the 30, 60, 125 and 250k nano devices available for immediate production.

Libero IDE version 8.5 supports RTAX-DSP FPGAs and enables DSP development for the first time on the RTAX family with the implementation of an 18 x 18bit mathblock.

The mathblock is available in the Libero IDE catalogue macro cell library and can be implemented with Smartdesign or user HDL.

The mathblocks can be managed through Libero’s standard synthesis, simulation and layout flows.

The embedded radiation-tolerant DSP mathblock supports simple signed 18×18 multiply, dual signed 9×9 multiply, multiply plus accumulate and cascaded multiply applications, enabling efficient implementation of DSP structures such as finite impulse response (FIR), infinite impulse response (IIR) digital filters, fast Fourier transforms (FFT) and inverse Fourier transforms (IFT), discrete cosine transforms (DCT), correlators and digital IF up/down converters.

RTAX-DSP offers high performance at densities of up to four million equivalent system gates and 840 user I/Os for space-based applications.

The RTAX-DSP family features up to 120 mathblocks, each capable of operating at 125 MHz over the full military temperature range (-55 to +125C) for a total throughput of 15 billion multiply/accumulates per second (15 GMACS).

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