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Russell Stapleton PhD will speak at the International Microelectronics and Packaging Society (Imaps) Arizona Chapter in Mesa on 26 August 2009.

Stapleton, senior staff scientist at Lord Corporation, will discuss Lord wafer-applied underfill for fine pitch devices.

Lord wafer-applied coatings and fluxing adhesives improve reliability while reducing costs associated with manufacturing Wafer Level Chip Scale Packing (WLCSP).

Stapleton will discuss the soon-to-be commercialised Lord Solderbrace solutions, which are stencil-printed or spin-coated onto the wafer and provide the final WLCSP passivation layer.

Solderbrace materials for WLCSPs are b-staged, photodefined and developed on the same tools currently used in high-volume photo-imaging processes.

Current limitations include fine pitch and maskless applications; however, second-generation wafer-level Solderbrace materials are now being developed to address applications such as flip chip and copper pillar/stud.

Lord is also developing non-traditional adhesives and coatings for chip assembly, die thinning, die bow correction, dielectrics and wafer bonding as well as partnering with wafer-level packaging companies to deliver custom solutions to high-volume applications.

Stapleton gained a PhD in polymer science from the University of Akron in 2004.

His background is in polymer synthesis, organometallics and kinetics.

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