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The LPC4000 range enables customers to develop applications such as motor control, power management, industrial automation, robotics, medical, automotive accessories and embedded audio.

Said to be the world’s first asymmetrical dual-core digital signal controller architecture featuring ARM Cortex-M4 and Cortex-M0 processors, the LPC4000 enables the development of DSP and MCU applications within a single architecture and development environment.

NXP will be showcasing the LPC4000 simultaneously at Electronica 2010 in Munich, Germany, from 9 to 12 November and at ARM Techcon, Santa Clara, California, from 9 to 11 November .

The LPC4000 range is targeted for microcontroller designers who want more efficient ways to tackle maths-intensive algorithms and DSP designers who feel constrained on peripherals.

The LPC4000 is also suitable for designers who want to upgrade from an existing DSC processor.

Its Cortex-M4 processor combines the benefits of a microcontroller – integrated interrupt control, low-power modes, low-cost debug and ease of use – with high-performance digital signal processing features such as single-cycle MAC, single-instruction multiple-data (SIMD) techniques, saturating arithmetic and a floating point unit.

The LPC4000 has an optimised 256-bit wide Flash memory architecture, which reduces power consumption with minimum memory fetches while maximising the performance of the Cortex-M4 processor.

It features a dual bank architecture that provides up to 1MB Flash for safe re-programming and flexible memory partitioning.

The LPC4000 offers 264kB SRAM, making it the largest available on any Cortex-M microcontroller.

A Cortex-M0 subsystem processor offloads many of the data movement and I/O handling duties that can drain the bandwidth of the Cortex-M4 core.

Having an asymmetrical dual-core gives developers the power, cost and system complexity savings of a one-chip solution – and allows them to more easily partition their software.

Configurable peripherals available on the LPC4000 include a State Configurable Timer, an SPI Flash Interface and a Serial GPIO Interface.

The State Configurable Timer Subsystem consists of a timer array with a state machine, enabling complex functionality, including event-controlled PWM waveform generation, ADC synchronisation and dead-time control.

The SPI Flash Interface provides a seamless high-speed memory-mapped connection to virtually all SPI and quad-SPI manufacturers.

NXP’s Serial GPIO, available for the first time on the LPC4000, allows a developer the flexibility to interface to any non-standard serial interface or to mimic multiple standard serial interfaces – such as I2S, TDM for multi-channel audio and I2C.

Additional peripherals on certain members of the range include two HS USB controllers, an on-chip HS PHY, a 10/100T Ethernet controller with hardware-enabled TCP/IP checksum calculation, and a high-resolution colour LCD controller.

Standard features on all products in the LPC4000 range include: 32kB ROM containing boot code and on-chip software drivers; AES-128 decryption (encryption is available on some products); eight-channel general-purpose DMA (GPDMA) controller; two 10-bit ADCs and 10-bit DAC with data conversion rate of 400,000 samples/s; a motor Control PWM and Quadrature Encoder Interface; four UARTs; two Fast-mode Plus I2C; I2S; two SSP/SPI; smart card interface; four timers; windowed watchdog timer; an alarm timer; an ultra-low power RTC with 256B of battery-powered backup registers; and up to 146 general-purpose I/O pins.

The LPC4000 is said to be the only Cortex-M4-based controller to have a pin-compatible Cortex-M3-based equivalent, allowing developers the flexibility of designing a system for a microcontroller (M3) or a DSC (M4) in the same footprint.

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