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Multi-gigabit baseband processor for wireless fibre applications

By Lattice Semiconductor on 17th February 2016

Product Details Supplier Info More products
Lattice - MULTI-GIGABIT BASEBAND PROCESSOR FOR WIRELESS FIBER APPLICATION

Lattice Semiconductor has announced availability of the company’s new baseband processor. The SB6541 is designed for use in conjunction with Lattice’s Sil6340 and SiI6342 RF transceivers to target fixed wireless access and wireless backhaul of urban broadband infrastructure such as LTE small cells and metro Wi-Fi access points.

Increasing demand for gigabit IP data to the home is driving demand for fixed wireless broadband access. In addition, in high data density areas, gigabit IP data connectivity is required for metro Wi-Fi and LTE deployments. The 60 GHz band is ideal for these applications due to the large bandwidth available and the unique propagation characteristics of the band that allow high spectrum reuse, both of which are essential for next-generation wireless network architectures. The chipsets offer the industry’s first complete solution in the 60GHz frequency band, leveraging SiBEAM technology for increased data throughput and network reliability.

Lattice’s chipsets also support beam-steering technology on phased array antennas. Devices that implement beam-steering require only rough alignment and can be installed quickly without specialized skills. A link can then be established between that node and other nodes in the network without manual intervention, and maintained even under changing environmental conditions or network reorganization. This significantly reduces installation and maintenance costs.

When used in combination with the Lattice Sil6342 RF transceiver, the SB6541 supports Internet Protocol (IP) data rates of up to 2 Gbps, with a typical throughput of 1 Gbps at a range of up to 300 meters. The device integrates with the RF transceiver via high-speed analogue I/O and a digital control interface. The SB6541 processor can be easily integrated into any system design through a PCIe interface.

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