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NXP Semiconductors has introduced a high-performance ARM Cortex-M3 microcontroller offering maximum connectivity and bandwidth options for a wide range of demanding applications.

The LPC1800 is optimised for low-power operation at very low frequencies all the way through to 150MHz maximum performance from either Flash or RAM.

The flexible dual-bank 256-bit wide Flash memories can be used for concurrent write/read operations, allowing ‘golden copy’ preservation and prevention of reprogramming mishaps, or simply used as a single bank of memory.

The LPC1800 also features two new peripherals: a flexible quad-SPI interface and a state-configurable timer subsystem.

Designed using NXP’s ultra-low-leakage 90nm process technology, the LPC1800 offers fast operation, low dynamic power consumption and low leakage optimisation yielding between 10 and 100 times reduction in standby modes.

The LPC1800 offers large on-chip SRAM, with up to 200KB provided in multiple banks, each with separate bus master access for higher throughput and individual power-down control for low-power operation.

The dual-bank 1MB Flash architecture provides high reliability in application reprogramming and allows for non-stop Flash operation.

NXP’s high-speed interface will connect with virtually all SPI and quad-SPI manufacturers.

High-speed interfacing from quad-lane SPI memories at up to 80Mbps per lane provides for much larger off-chip data and code execution than available from on-chip memories.

The LPC1800’s state configurable timer subsystem comprises a timer array with a state machine enabling complex functionality including event controlled PWM waveform generation, ADC synchronisation and dead time control.

This timer subsystem gives embedded designers increased flexibility to create user-defined waveforms and control signals for many applications including power conversion, lighting and motor applications.

Additional peripherals available on the LPC1800 include two HS USB controllers, an on-chip HS PHY, a 10/100T Ethernet controller with hardware enabled TCP/IP checksum calculation, a high-resolution colour LCD controller and AES decryption including two 128-bit secure OTP memories for key storage.

Versions with AES encryption are available on request.

Standard features on all members of the series include: 32KB ROM containing boot code and on-chip software drivers; eight-channel general-purpose DMA (GPDMA) controller; two 10-bit ADCs and 10-bit DAC with data conversion rate of 400k samples/s; a motor control PWM and quadrature encoder interface; four UARTs; two fast-mode Plus I2C, I2S; two SSP/SPI; Smart card interface; four timers; windowed watchdog timer; an alarm timer; an ultra-low power RTC with 256 bytes of battery-powered backup registers; and up to 80 general-purpose I/O pins.

NXP Semiconductors

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