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Apache Design Solutions has announced Pathfinder, a full-chip electrostatic discharge (ESD) physical integrity solution to address the reliability challenges faced by nanometer designs.

It delivers technologies in modelling, extraction and simulation for ESD verification, targeting early prototyping, circuit optimisation and full-chip signoff.

Pathfinder’s core technologies include: native handling of clamp-cell snap-back characteristic for dynamic SPICE-like simulation; built-in extraction and handling of large-scale power/ground RLC, substrate RC and package parasitics; layout-based full-chip analysis of ESD events such as Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM) ESD charging or discharging.

In addition, ESD clamp cell design and optimisation for custom I/O and analogue macro requires SPICE-like accuracy.

Pathfinder is a high-throughput solution with productivity advantages including: 100 million instances with overnight turnaround time for static ESD verification; hundreds of thousands of transistors block, including clamping devices for SPICE-accurate dynamic ESD simulation; layout-based debugging GUI environment for cross probing and ‘what-if’ analysis.

In addition, the use of multiple power and ground networks requires the inclusion of ESD protection circuitry inside the core of the chip.

At the full-chip level, Pathfinder verifies the placement and connectivity of ESD cells for HBM, MM and CDM, based on layout information and design rules.

It computes the impedance in the discharge path through the distributed power/ground and package mesh, and the participating clamp cells.

It verifies the effective resistance between pads/bumps to other pads/bumps; between pads/bumps to clamp circuits; between multiple clamp circuits; and between active devices and clamp circuits, for pass/fail check.

Increasing current flow through the metal layers of the discharging path can also cause electromigration (EM) induced damages to interconnects.

Pathfinder provides current density check for all power/ground metals, I/O nets and clamp devices, allowing the designers to verify that the current flow during discharge event is within the established limits.

Pathfinder can also simulate transistor-level netlist such as I/Os, PLLs and Serdes.

It incorporates eSIM, Apache’s proprietary simulator for ESD transient analysis, with SPICE-level transistor model.

eSIM can handle negative resistance in snap-back devices, which typically causes non-convergence and slow down in classic SPICE simulators.

In addition, eSIM, with its dedicated matrix solver, can handle large-scale power/ground, substrate and package mesh networks, including non-linear devices.

Pathfinder performs stress check across junction voltages of all transistors during the simulation to identify potential device failures due to ESD events, such as CDM.

To help with debugging and isolating circuit and layout issues resulting from an ESD event, Pathfinder provides a GUI environment with overlay of the simulation results on the layout.

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