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PLX Technology has announced that its entire Expresslane PCIe Gen 2 switch family, ranging from four to 96 lanes, is now fully compliant to support the Access Control Service (ACS).

ACS is required in PCIe switches in various input/output virtualisation (IOV) applications.

Virtualisation allows multiple operating systems running simultaneously within a single computer to share central-processing-unit (CPU) and input/output (I/O) resources.

The ACS capability in PLX PCIe switches prevents silent data corruption and unintended data transfers between partitions of shared resources in the virtual computing environments found in modern data centres.

Virtual computing is being increasingly deployed in data centres to reduce capital expenditures and operating expenses.

All PLX Gen 2 switches also support Alternative Routing-ID Interpretation (ARI), which increases the number of functions that a device may support.

In addition, PLX PCIe Gen 2 switches support Multicast (MC), which allows a single ingress packet to be sent to multiple egress ports, delivering a significant saving in CPU utilisation.

ACS, ARI and MC were announced as engineering change notices (ECNs) by the PCI-SIG and were later included in PCI Express Base Specification 2.1.

ACS defines a set of control points within a PCIe topology to determine whether a packet should be routed normally, blocked or redirected.

ACS is applicable to root complexes (RCs), switches and multi-function I/O devices.

In PCIe packets, routing IDs, requester IDs and completer IDs are 16-bit identifiers traditionally composed of three fields: an 8-bit bus number, a 5-bit device number and a 3-bit function number.

With ARI, the 16-bit field is interpreted as two fields instead of three and there are an 8-bit bus number and an 8-bit function number; the device number field is eliminated.

This new interpretation allows an ARI-enabled device to support up to 256 functions instead of eight, which allows higher device integration and provides better utilisation of server CPU for virtual machines or system images, according to the company.

MC defines the process for copying a single packet on an ingress port to multiple egress ports of a PCIe switch.

Multiple groups of ingress/egress ports can be configured for MC, thus providing additional flexibility in moving traffic or storing information.

PLX pioneered this idea in PCIe and helped define it for the PCI-SIG specification.

Today, the company offers 20 PCIe Gen 2 switch devices, with more in development.

These solutions include a large lane and port count switch (with 96 lanes and 24 ports) and, for more mainstream applications, a four-lane, four-port switch.

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