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PLX Technology has released a pair of high-performance PCIe switches for control planes, back planes, Gbit Ethernet cards, host bus adapters, servers, enterprise storage and multi-function printers.

The PLX Expresslane PEX 8617 (16 lanes, four ports) and PEX 8613 (12 lanes, three ports) are PCI-SIG PCIe 2.0 (Gen 2) specification-compliant switches with widespread applicability as an essential building-block for system expansion and performance enhancement.

The PEX 8617 and PEX 8613 feature the PLX-exclusive non-transparent (NT) port functionality.

An NT port isolates the address domains between two hosts, which in turn allows the switches’ dual virtual-channels (VCs) to provide two separate data paths for memory traffic (high and low priorities) with enhanced quality of service (QoS), regardless of CPU single VC limitations.

The two VCs benefit designs by establishing dual-buffer entities used to queue PCIe packets, thereby improving traffic performance.

The traffic class (TC) specifies priorities for a given PCIe packet and takes advantage of two VCs by sending high- or low-priority TC assignments, as opposed to the same priority for all packets found on a single VC chip.

Another PLX-only feature, integrated spread spectrum clock (SSC) isolation, provides the capability for isolating the clock domains of two systems.

SSC isolation allows designers the flexibility to develop products with asynchronous clock sources, thus removing the need for a single clock source for all PCIe components in a system.

Both switches are supported by PLX’s Visionpak software design kit (SDK).

This SDK is focused on getting designs to market faster and adds the ability to access internal data paths and state machines for debugging systems; a tool to measure Rx eye-width inside the device for validating signal integrity; a function to inject errors to check system behaviour; loopback Tx to debug data paths; and the capability for packet performance/activity monitoring.

The PEX 8617 and PEX 8613 feature the PLX Performancepak, which provides additional functions to designers to reach peak performance and includes read pacing to fairly allocate host-port bandwidth, along with dynamic buffer allocation, to absorb fluctuations in bandwidth demand.

Krishna Mallampati, PLX marketing director of PCIe switch products, said: ‘Applications including dual-host/multi-host, host-failover/redundant systems and intelligent I/O modules will benefit from these new PLX switches.

‘Every PLX Gen 2 device incorporates NT functionality, ten of which offer two VCs, and many designers have now come to expect integrated NT for their new designs to avoid the additional costs and performance loss of other solutions.’ PLX claims its PCIe switches provide board designers and system architects with the industry’s most extensive and proven lineup of products, ranging in density from three to 24 ports and from four to 96 lanes.

Detailed information on the entire Expresslane switch family is available from PLX’s website.

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