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Lattice Semiconductor has announced the availability of eight reference designs and two development kits for prototyping high-volume, low-power, space-constrained applications.

The company has launched a USD49 (GBP30) development kit for the ProcessorPM POWR605 power manager device and a USD69 development kit for the ISPMACH 4000ZE CPLD, the ISPMACH 4000ZE Pico Development Kit.

System designers at OEMs and ODMs are increasingly using programmable logic devices in their systems as they face time-to-market pressures and design flexibility requirements that cannot be addressed by ASICs and ASSPs alone.

Using Lattice’s programmable logic solutions, designers can now introduce several versions of the same product with very short development cycles and make upgrades to existing products in the field with low risk.

The second-generation ISPMACH 4000ZE CPLD family is said to be ideal for ultra low-power, high-volume portable applications.

The ISPMACH 4000ZE family offers typical standby current as low as 10uA; ultra-small, space-saving 0.4mm pitch ball grid array packages; 3.3V, 2.5V and 1.8V I/O standards support; and 5V tolerant I/Os.

Lattice’s ISPMACH 4000ZE CPLDs can be used for power management, level shifting and general-purpose I/O expansion.

The ProcessorPM (Processor Power Manager) POWR605 device monitors up to six circuit board power supplies and provides up to five open-drain digital I/Os.

The device can generate signals such as a CPU reset, including pulse stretching and power supply fault interrupt, using the on-chip 16 macrocell CPLD and four programmable timers.

There are also two general-purpose digital inputs, which can be used for other control functions such as manual reset input and watchdog timer input.

The ProcessorPM device is available in a 4 x 4mm, 24-pin QFNS package.

The ISPMACH 4000ZE Pico Development Kit is an easy-to-use, low-cost platform for evaluating and designing with ISPMACH 4000ZE CPLDs.

The kit is based on a 2.5 x 2in evaluation board that features the ISPMACH 4256ZE device in a lead-free 144-pin CSBGA package, a Power Manager II POWR6AT6 for power monitoring, LCD panel and an expansion header.

The Pico evaluation board provides features to help evaluate the use of the ISPMACH 4000ZE CPLD in the context of battery-powered, handheld application.

CPLDs are ideal for glue logic, level shifting between signal standards and providing additional interfaces for I/O limited microprocessors.

On-board power monitoring circuits with the POWR6AT6 device provide a convenient way to monitor power consumption of the CPLD.

A USB cable programming interface allows modification of the CPLD programming from any PC host.

By using ISPLEVER Classic and ISPVM software, designers can compile their own designs captured as VHDL, Verilog HDL or schematics.

The kit includes demonstration designs pre-programmed into the ISPMACH 4256ZE and POWR6AT6 devices that highlight key CPLD applications and power-saving measures to maximise battery life.

The CPLD demo design integrates an up/down counter, right/left shift register and an I2C bus master controller that communicates with the POWR6AT6.

An LCD panel displays demo output using three characters.

The ProcessorPM Development Kit is a versatile, ready-to-use hardware platform for evaluating and designing with ProcessorPM power management devices.

The kit is based on a 2.5 x 2in evaluation board that features the ProcessorPM POWR605 device in a lead-free 24-pin QFN package, a Power Manager II POWR6AT6, evaluation circuits that emulate a power supply bus and processor interface, and an expansion header.

The kit includes a preconfigured processor support demonstration design that will support hundreds of microprocessor, DSP, ASSP or ASIC power management scenarios.

The demo integrates three key support functions for a processor: voltage supervisor, watchdog timer (WDT) and reset generator.

The board is controlled with switches and push buttons.

A slide potentiometer emulates brown-out conditions on a 2.5V supply rail.

A pin header provides access to the voltage monitor inputs and digital IOs of the ProcessorPM device and the I2C and power supply margin/trim IOs of the POWR6AT6 device.

Users may extend or modify the pre-configured demo using PAC-Designer and ISPVM software.

The kit includes a processor support demo that shows the versatility of the pre-configured ProcessorPM design by allowing modification of the WDT expiration period and reset pulse enable/disable with DIP switch settings.

Users can then emulate supply rail conditions, manual reset inputs and the processor interface with push buttons and a slide potentiometer.

The board indicates reset, interrupt and IO states with LEDs.

If supply rails go out of tolerance, a manual reset occurs or, if the WDT period expires, the ProcessorPM device will assert processor control signals to indicate reset or WDT interrupt.

Lattice Semiconductor

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