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Ansys subsidiary Apache Design has launched RTL Power Model (RPM), a technology designed to optimise a range of power-sensitive applications, such as ultra-low-power electronics.

The technology is said to accurately predict integrated circuit (IC) power behaviour at the RTL level with consideration for how the design is physically implemented.

As a result, the technology helps to enable chip power delivery network (PDN) and IC package design decisions early in the design process, as well as to ensure chip power integrity sign-off for sub-28nm ICs, the company claims.

As a new offering to Apache’s Powerartist-XP software, RPM’s core technologies include Powerartist Calibrator and Estimator (PACE) for accurate power estimation at the RTL level prior to the availability of physical layout, as well as a Fast Frame-Selector for critical power-aware cycle selection.

RTL Power Model technology designed to optimise power-sensitive applications

Ansys subsidiary Apache Design has launched RTL Power Model (RPM), a technology designed to optimise a range of power-sensitive applications, such as ultra-low-power electronics.

The technology is said to accurately predict integrated circuit (IC) power behaviour at the RTL level with consideration for how the design is physically implemented.

As a result, the technology helps to enable chip power delivery network (PDN) and IC package design decisions early in the design process, as well as to ensure chip power integrity sign-off for sub-28nm ICs, the company claims.

As a new offering to Apache’s Powerartist-XP software, RPM’s core technologies include Powerartist Calibrator and Estimator (PACE) for accurate power estimation at the RTL level prior to the availability of physical layout, as well as a Fast Frame-Selector for critical power-aware cycle selection.

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