Product Details Supplier Info More products

Silicon Laboratories has introduced a frequency-flexible timing IC solution for networking and telecoms applications that require jitter attenuation for clock signals without clock multiplication.

The Si5317 pin-controlled jitter cleaning clock IC provides jitter filtering to remove unwanted noise and produces low-jitter outputs for a range of applications, such as wireless backhaul equipment, DSLAMs, multi-service access nodes (MSANs), GPON/EPON optical line termination (OLT) line cards and 10GbE switches and routers.

As networking and telecommunications hardware designs migrate to higher speeds and greater complexity, timing architecture has become a key consideration in the overall system design.

Managing clock jitter is said to be critical in high-speed applications, since this noise degrades overall system performance, affecting the design’s bit error rate (BER) and signal-to-noise ratio (SNR).

The Si5317 clock cleaner provides a simple, flexible and cost-effective jitter filtering solution for these performance-sensitive applications, according to Silicon Laboratories.

The Si5317 effectively removes unwanted noise on any clock frequency from 1MHz to 710MHz and produces two ultra-low-jitter output clocks at the same frequency as the input.

Unlike traditional clock ICs or discrete phase-locked-loop (PLL) module solutions requiring multiple components to support different frequencies, one Si5317-based design and layout supports jitter attenuation for any 710MHz (or less) clock signal, enabling design reuse across multiple applications.

Designers can use simple pin settings to configure the frequency range and PLL bandwidth, eliminating the need for firmware and serial programming, which are required by traditional clock IC solutions.

‘The Si5317 simply drops into the clock path to provide jitter attenuation on clock signals up to 710MHz without requiring firmware configuration or BOM modifications to accommodate different frequencies,’ said Mike Petrowski, general manager of the company’s timing products.

Based on Silicon Laboratories’ patented DSPLL architecture, the Si5317 clock cleaner delivers 0.29ps RMS jitter performance, improving BER and SNR in jitter-sensitive applications.

This jitter performance enables a portion of the system jitter budget to be allocated to other devices, simplifying component selection and clock tree design.

The Si5317 is said to integrate a single supply voltage regulator with excellent power supply noise rejection.

This streamlined power supply design eliminates the need for multiple supply rails and discrete ferrite beads.

On-chip power regulation also minimises the board design’s sensitivity to high-speed noise and switching power supplies, reducing the risk that the power supply noise might affect the design’s overall jitter performance.

The Si5317 does not require any external PLL components, simplifying PCB design and layout in space-constrained applications while minimising the threat of board-level noise affecting jitter performance.

On-chip DSPLL technology eliminates the need for a charge pump and/or loop filter design required by traditional VCXO-based PLL modules and clock ICs.

This integration minimises design time and development risk by guaranteeing loop stability and jitter performance across temperature, process and voltage variation.

Combining all PLL components into a single device also eliminates sensitive noise entry points between discrete PLL components, improving immunity to board-level noise.

In addition to jitter attenuating clocks, the company’s range of mixed-signal timing ICs includes programmable XO/VCXOs, CMOS-based silicon oscillators, clock generators, low-jitter clock multipliers, buffers and physical layer timing devices.

The Si5317 clock cleaner can be combined with many of these timing devices to enable a complete, ultra-low-jitter timing solution.

Companion timing IC products for the Si5317 include the Si500 silicon oscillator, the Si5338/34 710MHz differential clock generators, the Si5355/56 200MHz CMOS clock generators and the Si5330 low-jitter clock buffers.

The Si5317 connects to any of these timing ICs to provide two ultra-low-jitter output clocks.

Samples and production quantities of the Si5317 clock cleaner are available now.

Pricing in 10,000-unit quantities starts at USD6 (GBP4).

The Si5317-EVB evaluation board is available now for USD125, providing a user-configurable platform for evaluating the Si5317 jitter cleaning clock.

Silicon Laboratories

View full profile