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Traceanalyzer 1.2 is said to deliver a tenfold speed improvement in terms of visualising and analysing timing trace and log data for ECUs, controllers, processors, buses and networks.

Also claimed to reduce memory requirements tenfold, the Symtavision Traceanalyzer enables the visualisation of system timing in terms of the constituent ECUs, controllers, processors, buses and networks.

With traces imported from standard trace probes, it visualises the trace and analyses the timing so that key timing parameters can be identified and properly understood, and generates statistics on execution times, interrupt patterns, communication bursts and resource utilisation.

It provides visual clarity showing controller and bus schedules with events, blocking and pre-emptions and details the timing chains so that engineers can see the flow of signals and data through the system including data loss and multiple reads of the same data.

Results are provided graphically and in tabular form.

Symtavision Traceanalyzer is also capable of automatically generating system timing models for SymT, Symtavision’s de-facto industry-standard tools suite for system-level timing design and timing verification.

Symtavision recently announced SymT 2.4, incorporating a wealth of new and improved features targeted at the automotive electronics, aerospace, automation and transportation markets including enhanced support for multi-core processors and Autosar.

In the coming months, Dr Jersak, chief executive officer of Symtavision, will be giving talks on the techniques and tools for system-level timing design and timing verification at SAE World Congress 2011 (13 April Detroit), ESC 2011 Silicon Valley (5 May San Jose) and DAC 2011 (5 June San Diego) in the US.


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