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A bonded silicon-on-sapphire (SOS) substrate developed by Peregrine and Soitec has been qualified for use in manufacturing Peregrine’s next-generation STeP5 UltraCMOS RF IC semiconductors.

Soitec’s core direct wafer-bonding technologies, combined with Peregrine’s legacy SOS process development and IC design expertise, enabled the development of a tuned substrate that delivers the RF performance required by the mobile wireless and industrial markets.

The substrate is a bonded monocrystalline SOS substrate jointly engineered by the two companies.

Soitec’s process expertise and direct wafer-bonding technologies were utilised to transfer and bond a high-quality, monocrystalline thin silicon layer onto a sapphire substrate.

The resulting bonded silicon layer offers improvements in transistor mobility and silicon quality beyond conventional SOS wafers that utilise an epitaxially grown silicon layer, according to the companies.

The substrate provides Peregrine with an ideal design landscape for enhancements in RFIC performance, functionality and form factor, enabling an IC size reduction and performance increase by as much as 30 per cent.

It also enables Peregrine to continue its long-term strategy toward highly integrated RF Front-End (RFFE) IC solutions in a substrate technology that matches the yield and scalability qualities of bulk silicon technologies.

Peregrine Semiconductor

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