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Atrenta has announced that Fujitsu Microelectronics Europe has adopted its Spyglass-CDC to help reduce the design risks associated with its complex system-on-chip (SoC) designs.

Early design closure solutions from Atrenta are said to allow design capture, verification, optimisation and exploration early in the design flow at the register transfer language (RTL) stage, when it is faster and easier to correct problems and explore alternatives.

This approach facilitates propagation of design efficiencies to detailed, back-end implementation with minimised schedule risk.

Atrenta’s Spyglass-CDC product analyses SoC designs to ensure that complex clock synchronisation schemes, such as Fifos and handshakes, are correct.

Bugs in fault clock domain synchronisations between IP blocks on a chip are hard to find with conventional design tools and represent a leading cause of chip re-spins and field reliability issues.

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