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Sundance has extended its partnership with Cadre Codesign to deliver Cadre’s CT-JPEG04 core across a range of it’s modular DSP FPGA multiprocessor hardware solutions.

Based on the Jpeg ISO/IEC IS 110918-1 standard image-compression algorithm, the core compresses images of 1280 x 1024 pixels resolution at a rate of 500 frames/sec and can sustain an input of one 8-bit pixel every 660MHz.

This level of performance makes the solution suited to applications where images are analysed on the fly or stored for later reference and analysis.

The Cadre Codesign core significantly outperforms off-the-shelf Jpeg cores that can typically sustain inputs of 4MB frames at 30 frames per second and generate outputs of 122MB/sec.

Provided with a Modelsim evaluation model the core will be initially available on Sundance’s digital video infrastructure platform (DVIP).

Built on Sundance’s modular and scalable multiprocessing concept, the DVIP uses the performance and flexibility of two TI TMS320C6455 digital signal processors (DSP) and a TMS320DM642 DSP-based digital media processor.

The 1GHz C6455 DSPs allow multiple processors to be connected via a serial rapid I/O (SRIO) interface and the DVIP incorporates Xilinx Virtex-4 FX60 FPGAs that are the implementation target for Cadre’s CT-JPEG04 core.

The modular architecture of the DVIP allows customers to increase the processing performance in the field and add one of more than 40 additional variant modules that support the Sundance TIM (Texas Instruments Module) standard.

Design support is provided via 3L’s Diamond multiprocessor tool-suite, which provides a highly-automated development flow from concept through to applications running in multiprocessor hardware and Code Composer Studio from TI.

The agreement with Cadre broadens the Sundance offer to application developers targeting high-end video and imaging systems and is another addition to the IP ecosystem that supports Sundance’s multiprocessing platforms.

Sundance Multiprocessor Technology

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