Product Details Supplier Info More products

Synopsys has enhanced its Designware IP for the ARM AMBA 3 AXI interconnect with a hybrid architecture implementation.

This has enabled dedicated high performance and shared low performance channels to be combined within a single AMBA 3 AXI on-chip interconnect.

This new architecture, available in synthesisable source RTL, allows designers to configure the bus fabric to eliminate unnecessary logic within the design, reducing area, power consumption and overall routing congestion.

The hybrid architecture is ideal for system on chip (SoC) designs that use a native AMBA 3 AXI interconnect.

It also reduces the area impact for SoC designs transitioning from an AMBA 2.0 AHB to an AMBA 3 AXI-based architecture.

As demands on system performance continue to increase, the effective control of bandwidth allocation for SoC peripherals becomes more important.

The bandwidth requirements for each master-to-slave link within a system can vary widely.

Traditional off the shelf bus-architectures consist of either a single shared-bus that services all master and slave devices, or dedicated buses that service specific master and slave devices.

These bus architectures do not allow designers to configure the interconnect to accommodate individual component requirements.

The hybrid architecture implemented in the Designware IP for the AMBA 3 AXI interconnect provides designers with a choice of connecting the master-to-slave link through either a shared or dedicated bus within a single AMBA 3 AXI on-chip bus interconnect.

This flexibility helps designers reduce the number of dedicated buses and wires in the system, alleviating routing congestion, minimising area and lowering power consumption.

The architecture eases timing closure by allowing for greater control of the critical paths throughout the bus interconnect.

In a recent case-study using the Galaxy Implementation Platform, Synopsys configured the Designware IP for AMBA 3 AXI interconnect fabric consisting of 10 master and 10 slave ports.

The hybrid architecture allows the low-bandwidth master-slave links of the dedicated bus to be replaced with a shared bus, while keeping the high-bandwidth master-slave links as dedicated buses.

With this implementation, Synopsys was able to reduce the number of wires by 52 per cent, area by 30 per cent, and power consumption by 30 per cent when compared with Synopsys’s traditional Designware IP for the AMBA 3 AXI interconnect fabric without the hybrid architecture.

The hybrid architecture has been verified using Synopsys Designware Verification IP for the AMBA 3 AXI interconnect, which has earned the ARM AMBA 3 Assured logo certification.

Certification lowers integration risk and gives designers confidence that their AMBA 3 AXI interconnect-based designs using the Designware IP will accurately adhere to the AMBA 3 AXI protocol specifications as defined by ARM.

The Designware IP for the AMBA 3 AXI interconnect provides internal piping options, allowing designers to balance the operating frequency and latency requirements without incurring a throughput penalty.

View full profile