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Tektronix has announced an addition to what it claims is the industry’s most comprehensive solution for PCI Express 3.0.

The offering provides physical layer transmitter (Tx) verification, debug, characterisation and compliance testing using Tektronix DPO/DSA/MSO70000 Series oscilloscopes.

The PCIe 3.0 architecture provides a low-cost, high-performance I/O technology that includes a new 128b/130b encoding scheme and a data rate of 8GT/s, doubling the interconnect bandwidth over PCIe 2.0.

Based on the same board material (FR4) and connectors as previous generations, PCIe 3.0 represents a more difficult test challenge with smaller margins and new jitter measurements required to account for increased signal loss in the channel.

Coupled with Serial Data Link Analysis (SDLA) software, Tektronix PCIe 3.0 solution (Option PCE3) provides a complete solution for verifying transmitter and channel performance of PCIe 3.0 designs and provides support for both the PCIe 3 Base Specification and CEM Specification measurements.

The electrical testing support provided by the new Option PCE3 solution complements the Tektronix TLA7SA16 and TLA7SA08 Logic Protocol Analyzer modules, bus support software and probes announced earlier this year that bring PCIe 3.0 logical and protocol testing support to the TLA7000 Series high-performance logic analyser range.

With over-sampling performance at 100GS/s, DPO/DSA/MSO70000 Series oscilloscopes deliver the performance and signal fidelity required to meet PCIe 3.0 test challenges.

Option PCE3 for these instruments accelerates the analysis and validation of PCIe designs and provides the flexibility to check devices for precompliance or perform device characterisation or debug in a single software package.

Serial Data Link Analysis software enables channel de-convolution, convolution and receiver equalisation.

DPOJET Jitter and Eye-diagram Analysis software provides jitter, eye-diagram and parametric testing.

And the P7520 Trimode Differential Probe is available for validation and debug of chip-to-chip links, including common mode measurements.

Performance validation and stress testing of PCI Express 3.0 receiver designs will also be critical given the large speed increase in the standard.

The Bertscope BSA85C provides stressed pattern testing with jitter and interference added to determine effective Bit Error Ratio from new receiver designs.

The Bertscope is complemented by the DPP125B, which adds critical pre-emphasis to the stressed pattern, and the CR125A that recovers the embedded clock to allow for eye diagram analysis on the resulting signal.

Bertscope provides a true Bit Error Ratio in addition to eye diagram analysis for complete debug of PCIe3.0 receivers.

These tools integrate with the TLA7SA16 and TLA7SA8 Logic Protocol Analyzer modules to provide complete visibility of PCIe 3.0 physical and logical layers.

The combination of the two solutions allows for rapid PCIe 3.0 digital debug and validation, analogue validation, compliance testing and device characterisation.

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