Product Details Supplier Info More products

Tensilica has introduced the low-power ConnX D2 16-bit dual-MAC DSP engine for its Xtensa LX dataplane processor cores for SOC (System-on-Chip) designs.

The ConnX D2 DSP engine provides performance from C code so that virtually any C program, including those written with C-intrinsic functions for the TI C6x family or ITU reference code, can run unmodified on the ConnX D2 DSP engine.

With a large ITU software code base, the ConnX D2 DSP engine is suitable for telecom infrastructure and VoIP applications.

Its small size (less than 70,000 gates) makes the customisable engine suitable for a variety of low-power portable consumer applications including mobile wireless devices, next-generation disk drives and data storage, home-entertainment devices and computer peripherals.

Tensilica’s Xtensa C/C++ compiler (XCC) produces instruction streams for the ConnX D2 DSP engine directly from C code.

Directly compiling C-code without the need for extensive iterations at the assembly code level offers designers a shorter development cycle.

The system also offers users a large existing library of code immediately on the ConnX D2 DSP engine.

The ConnX D2 DSP engine option adds dual 16-bit MAC units and an eight-entry, 40-bit register file to the base architecture of the Xtensa LX DPU.

The engine uses two-way SIMD instructions to provide high performance on vectorisable C code and includes an improved form of VLIW, allowing for parallelisation of code across the two MACs/ALUs when vectorisation is not feasible.

The ConnX D2 DSP engine supports a range of data types (e.g, 16-, 32-, and 40-bit integer and fixed point; 16-bit complex; eight- and 16-bit vector), seven addressing schemes and data-manipulation instructions including shifting, swapping, and logical operations for DSP algorithms.

For specific DSP algorithm acceleration, the ConnX D2 engine instructions include Add-Compare-Exchange (used with Viterbi), Add Modulo, Add Subtract, and Add Bit Reverse Base.

Used in conjunction with a bit-reversed addressing scheme, this instruction set delivers efficient FFT implementations.

The ConnX D2 SIMD unit is supported by a set of instructions for vector loads and stores that support multiple data widths and SIMD data register loading orders, which can be aligned or unaligned.

Designers can add multi-cycle execution units, registers and register files using the automated Tensilica Instruction Extension methodology.

Every Xtensa LX DPU is automatically generated with a complete set of software development and modelling tools matched to the DPU configuration.

From Xtensa Xplorer, designers can profile their application code and make the changes in the processor necessary to speed up that code.

Designers can also choose options for processor interfaces, memories, operating systems support, EDA scripts, debug and trace.

Tensilica also provides a collection of code generation and analysis tools that speed up the software application development process.

The Xtensa processor with the ConnX D2 DSP engine can deliver clock speeds up to 600 MHz in 65nm GP and can occupy as little as 0.18mm2 (fully routed) in 65GP process technologies.

View full profile