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By delivering AMBA 4 AXI4-compliant IP support, Xilinx’s ISE Design Suite 12 software enables the design of plug-and-play FPGAs.

The suite also provides advances in timing-driven design preservation, ‘intelligent’ clock-gating technology that reduces dynamic power consumption by up to 30 per cent and a design flow with fourth-generation partial reconfiguration capabilities that lowers system cost for a range of high-performance applications.

With full production support for all Xilinx Virtex-6 and Spartan-6 FPGA ranges, the ISE 12 release is said to be the industry’s only domain-specific design suite with interoperable design flows and tool configurations for logic, digital signal processing (DSP), embedded processing and system-level design.

In addition, Xilinx incorporated a number of software infrastructure and methodology enhancements that improve run time, streamline system integration and expand IP interoperability across its latest generation device ranges and targeted design platforms.

ISE Design Suite 12’s clock-gating technology includes fully automated analysis and fine-grain (logic slice) optimisation capabilities that have been developed to reduce the number of transitions.

The technology works by analysing designs using a series of algorithms to detect sequential elements within each FPGA logic slice that do not change downstream logic and interconnect when toggled.

The software generates clock-enable logic that automatically shuts down the unnecessary activity at the logic slice level to accumulate power savings without having to shut off an entire clock network.

Advanced design preservation capabilities in the ISE 12 design suite enable designers to reach design closure fast with repeatable timing results.

Designers can partition designs to focus on achieving required timing for critical blocks and lock those blocks to preserve placement and routing while they work on the rest of the design.

To foster plug-and-play FPGA design, Xilinx is standardising IP interfaces on the open ABMA 4 AXI4 interconnect protocol, which eases integration of IP from Xilinx and third-party providers, and maximises system performance.

Xilinx also worked with ARM to define the AXI4, AXI4-Lite and AXI4-Stream specifications for efficient mapping into its FPGA architectures.

Partial reconfiguration technology allows the dynamic modification of FPGA logic blocks by downloading partial bit files without interrupting the operation of the remaining logic.

ISE Design Suite 12 makes this technology easy to use with Xilinx FPGAs by providing an intuitive interface and simplified methodology that closely aligns with the standard ISE design flow.

The ISE partial-reconfiguration flow uses the same Xilinx tools and techniques for timing closure, design management and floorplanning, and design preservation.

Support for fourth-generation on-the-fly partial-reconfiguration technology enables designers to reduce system cost and power consumption by fitting applications into the smallest possible device.

Developers of next-generation wired Optical Transport Network (OTN) solutions can implement a 40G multi-port muxponder interface with one-third fewer resources as compared to devices without partial reconfiguration.

A range of other applications, including software-defined radio, also benefit from the increased flexibility provided by on-demand reconfiguration with Xilinx FPGAs.

The ISE 12 suite works with the latest simulation and synthesis software from Aldec, Cadence Design Systems, Mentor Graphics and Synopsys.

The 12.1 software features an average of 2x faster logic synthesis and 1.3x faster implementation run times for large designs than previous versions and an improved embedded design methodology.

It also includes an expanded offering of production qualified IP for the Virtex-6 FPGA Multi-mode Radio Targeted Design Platform, Spartan-6 FPGA Industrial Automation and Industrial Imaging Targeted Design Platforms, as well as the Virtex-6 HXT FPGA 100G OTN and Packet Processing Targeted Design Platform that will be available later this year.

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