Take the strain

AMD and IBM have perfected a new strained silicon transistor technology aimed at improving microprocessor performance and power efficiency.

The new process results in an approximate 24% transistor speed increase, at the same power levels, compared to similar transistors produced without the technology.

In addition, this process makes AMD and IBM the first companies to introduce strained silicon that works with silicon-on-insulator (SOI) technology, which provides additional performance and power savings benefits.

The new strained silicon process, called “dual stress liner,” enhances the performance of both types of semiconductor transistors, called n-channel and p-channel transistors, by stretching silicon atoms in one transistor and compressing them in the other. The dual stress liner technique works without the introduction of challenging, costly new production techniques, allowing for its rapid integration into volume manufacturing using standard tools and materials.

AMD and IBM researchers claim to the the first in the industry to simultaneously enhance the performance of both types of transistors in a semiconductor using conventional materials.

AMD plans to ship 90nm AMD Athlon 64 products that use the new strained silicon technology beginning in the first quarter of 2005. AMD also plans to gradually integrate it into all of its 90nm processor platforms, including its multi-core AMD64 processors.

IBM expects to introduce the technology on multiple 90nm processor platforms, including its Power Architecture-based chips, in early 2005.

Details of the AMD-IBM dual stress liner innovation were disclosed at the 2004 IEEE International Electron Devices Meeting in San Francisco, CA from December 13-15, 2004. The dual stress liner with SOI technology was developed by engineers from IBM, AMD, Sony and Toshiba at IBM’s Semiconductor Research and Development Center (SRDC) in East Fishkill, NY, as well as engineers from AMD at its Fab 30 facility in Dresden, Germany.

IBM and AMD have been collaborating on the development of next-generation semiconductor manufacturing technologies since January 2003.