Thanks for the memory

Synopsys, a developer of semiconductor design software, is to acquire Monolithic System Technology and Accelerant Networks in two multi-million dollar deals.

Synopsys is to acquire Monolithic System Technology (MoSys) in a cash and stock transaction valued at approximately $432 million (approximately $346 million net of cash).

Adding MoSys’ unique, patented 1T-SRAM technology to Synopsys’ DesignWare IP portfolio will provide Synopsys customers with memory IP that works with regular digital processes.

‘MoSys and Synopsys share a common goal of making it as easy as possible for engineers to adopt and use IP so that they can focus on their value-added technology,’ said Fu-Chieh Hsu, president, CEO and chairman of the Board for MoSys. ‘Through this acquisition, all SoC designers will be able to readily take advantage of our patented embedded memory technologies.’

The acquisition will be effected by means of an exchange offer to acquire all of the outstanding shares of MoSys for a purchase price of $13.50 per share, half of which is payable in Synopsys common stock and half in cash.

Synopsys has the option, exercisable not less than two business days before expiration of the offer, to pay the entire purchase price in cash. The acquisition is subject to certain conditions, including the tender of a specified number of the shares of MoSys, receipt of regulatory approvals, and other customary conditions. Synopsys intends to assume all outstanding MoSys stock options in the transaction.

The boards of directors of both companies have approved the transaction. In addition, certain of MoSys’ shareholders, including its executive officers and directors, who collectively own approximately 29% of the outstanding shares of MoSys, have agreed to tender their shares to Synopsys in the transaction.

The acquisition is expected to close before the end of May 2004.

In addition, Synopsys announced that has acquired Accelerant Networks, a privately held company that has developed the technology to build high-speed serial interfaces.

Synopsys intends to apply Accelerant’s SERDES (serializer-deserializer) technology to offer multiple standards-based PHY cores such as PCI Express, Serial ATA (SATA), and emerging 6.25 to 10Gb/sec backplane applications that use Accelerant’s binary and PAM4 (pulse amplitude modulation) signalling technologies. By combining these SERDES-based cores with Synopsys’ complementary digital cores, Synopsys will be able to offer customers integrated analog and digital IP solutions.

‘Accelerant’s underlying technology for high-speed serial interfaces is complementary with Synopsys’ digital logic cores,’ said Ken Molitor, president and CEO of Accelerant.

The terms of the Accelerant acquisition were not disclosed.