Today, miniaturisation is one of the most relentless pressures in the electronics industry. Consumers want ever smaller products, and at the same time they want each successive generation of products to deliver higher performance, consume less power and cost less money.
This is a tough nut to crack, and the responsibility for cracking it lies with the designers and manufacturers of the chips which lie at the heart of electronic devices.
Indeed, silicon vendors have made many advances. Take the steady reduction of chip geometry. Today, several companies are already working at geometries of 0.18µ, and some are producing products designed at an even smaller scale.
Developments like this have enabled the emergence of concepts such as the SOC (System On a Chip): a chip which integrates all of the system elements – microprocessor core, memory, logic, communications etc – onto a single piece of silicon. This approach is more space efficient than the use of discrete chips, and also offers performance and power advantages.
But, while smaller geometries promise much in theory, they also present such a significant design challenge.that current tools are increasingly inadequate. Today, it is no exaggeration to say that, at 0.18µ, as much as half of a chip’s performance is left on the table as a direct result of the implementation of current design orthodoxy. Worse, unless the industry accepts a radical reappraisal of this orthodoxy, there is little prospect of improvement.
But, before you reach for the scotch in despair, there is some good news. A new approach is available which has turned conventional design wisdom on its head and will underpin the next generation of SOC designs.
To appreciate the significance of this tool we must be clear on one of the most important issues facing chip designers. This is timing closure – the process of achieving target chip performance after final physical layout. In today’s complex, high-speed designs, this is a difficult task. However, the semiconductor and EDA (Electronic Design Automation) community has invested enormous amounts in developing toolsets to address the issue, and it can be done reasonably effectively. At least, it can be done reasonably effectively on geometries above 0.18 micron. The problem is that, as geometries shrink to smaller UDSM (ultra-deep sub-micron) levels, current physical design tools cannot cope. Why is this? Well, the key to timing closure is to control the critical signal paths in a chip. This delay derives mostly from the capacitative loading of the interconnect on the logic which drives it. And herein lies the problem. All major physical design flows today start with the known logical structure of the design and try to ‘estimate’ what this loading will turn out to be. They then add gate and buffer drive until they’re sure they’ve overdriven everything which might cause trouble.
The difficulty is that the ‘estimate’ extensions – initially using wireload models, and more recently placement-based wirelength estimates, don’t work properly at advanced geometries. Below 180 nanometers, most wire capacitance is determined by neighbouring wires, and increasingly by the actual signals on those wires determined in the last stages of detailed routing. As a result, estimate-based methods invariably rely on severely pessimistic loading assumptions (over-design) to eliminate all possible timing violations.
How much over-design occurs? At 180 nm, 30 to 50% of a chip’s performance is left on the table. In competitive markets, this is a prohibitive sacrifice. At Sequence we call this corrupt by ‘construction.’
The solution is simple: abandon those estimates. Nanometer timing closure requires interconnect-driven, not logic-driven methods. The fundamental problem is that uncertainty in wire capacitance leads to crippling over-design. The first point in the design flow where the wire geometry can be known with certainty is after detailed routing is complete. Timing closure problems can be solved for high-performance design after synthesis and place-and-route. Interconnect-driven methods will consistently produce faster chips than estimate-based mechanisms.
But how can we change interconnect without new routing iterations? The key is that timing closure really affects only a fraction of the chip, but what fraction? Since estimation methods can’t quantify loading, they can’t tell which wires are really the problem, and therefore must rework so much of the chip that the problem becomes large. But with exact interconnect and delay knowledge, careful optimisation can deliver both fast chips and rapid design closure, without rerouting.
This leads to the radical corollary that all this rewriting of standard physical EDA might really be unnecessary. Not that synthesis and place-and-route are obsolete; gates still need to be created, placed and connected. But the core goal of timing closure will be addressed by post-layout, interconnect-driven timing optimisers, which will surgically restructure wire topology and drive, without requiring place-and-route changes — not by more synthesisers and more routers.
To enable designers to implement this shift in design philosophy, Sequence has introduced Copernicus, the first interconnect-driven timing closure solution.
Copernicus has full visibility into the actual layout topology. A powerful, post-layout optimisation tool, Copernicus uses a patented methodology to identify timing ‘hot spots’ and then surgically corrects them in one direct pass, while maintaining the integrity of the routed signal nets. At the heart of the tool lies the ExactTopology engine which orchestrates Copernicus’s sub-engines: true 3-D extraction technology, advanced delay calculation and user-constraint driven static timing analysis. These work in incremental concert to continually ensure accurate interconnect modelling on all signal nets, associated capacitive loading and consequent timing delays. The result: elimination of setup timing violations and design rule violations in one smart pass through the tool, more aggressive chip performance and reduction in design size.
A major benefit to this approach is to have design teams continue to use their choice of synthesis, placement and routing flows and ‘dropping-in’ Copernicus to close timing. This allows synthesis to concentrate on its strength: deriving efficient logic structures, rather than estimating post-layout coupling-capacitive loading effects. It also allows routing tools to work on producing better routability and die area, extending the life of what these tools were originally meant to do.
At 0.25um design teams are having a hard time meeting performance requirements due to the ‘guardbanding’ of present tools. The Sequence timing closure approach allows designers to protect their current investment in synthesis, place and route. At the same time, design teams can avoid the trap of estimating routing effects. By operating after routing, this approach can see the exact effects of the 3D topology and make local, precise changes to unclog and fix real timing bottlenecks. This new approach takes advantage of acheivable silicon performance and produces faster designs, with far fewer design iterations.
Sidebar: The quest for closure
Sequence was formed six months ago with the merger of Frequency Technology and Sente. Frequency first introduced Copernicus in 1999 alongside a tool for clock tree analysis. This release of Copernicus is based on these earlier tools.
Timing closure is an oft used term to describe the problems when post layout design does not meet the required timing criteria. The designer must then go back into the design to correct the problem areas. But this often disturbs other circuits causing further timing problems. Achieving perfect ‘closure’ is the aim.
Sequence’s tool runs a 3D analysis of the wire capacitances of the final routing. This provides an accurate measure of delays and pinpoints their position. 3D capacitance isn’t known until after final routing, especially when you are dealing with line widths of 0.18 micron and below. This final step is a patent pending algorithm that repairs problems without requiring re-layout of the overall chip. See US patent 5901063 — ‘System and method for extracting parasitic impedance from an integrated circuit layout.’ The algorithm makes the specific changes to placement and routing while keeping the space for wires electromagnetically neutral.
Timing closure is the bane of the logic designer’s existence. At 0.18-micron feature sizes, the smooth succession from high-level design to physical design is increasingly impossible. Logic designers are forced to learn more about physical design, and the industry is pressed to provide technology to help them.
Perfect closure can only really happen when a physical synthesis links logic design and layout design. It should update the traditional design flow by bringing key physical functions into the front-end process. Logic decisions will be based on accurate interconnect delay estimates derived from the placement, while placement is driven by the timing constraints imposed by the logic configuration. RB
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