Infineon Technologies and IBM have presented what they describe as the world’s first 16 Mbit Magnetoresistive Random Access Memory (MRAM), a memory technology that uses magnetisation rather than electric charges to store bits of data.
This new non-volatile memory chip is said to be the highest density MRAM reported to date, demonstrating that MRAM has the potential to become a universal memory for high performance computing and mobile applications.
The increasing number of mobile applications such as smartphones and notebooks with additional multimedia features results in the need for more advanced memory chips. MRAM is a promising candidate for universal memory in high-performance and mobile computing as it is faster and consumes less power than existing technologies.
The time required to write the first bit of information into an MRAM chip is about one million times faster than the time required for a flash memory chip. The time required to read the first bit of information out of an MRAM chip is about three times faster than a NOR flash chip and about a factor of 1000 faster than in a NAND flash chip. Additionally, MRAM requires much less power in comparison to DRAM technology.
“Advances in high-performance computing have increased the demand for more innovative, powerful and versatile memory technologies,” said Dr T C Chen, Vice President Science and Technology, IBM Research. “IBM is constantly looking for new ways of improving server performance and MRAM could prove to be a powerful component.”
The 16Mbit MRAM product demonstrator is realised in a 0.18µm micron logic based process technology. It utilises a 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) cell and features an SRAM-like interface which is prevalent in mobile and handheld applications and well suited to the operation of the MRAM core.
The chip was designed to operate at access and cycle times of 30-40ns. Among published multi-Mbit MRAMs, this new MRAM chip is distinguished by the highest density (16Mbit) accomplished with a cell size of 1.42µm2. The multi-Mbit MRAM design also uses a novel bootstrapped write driver circuit and several design features to reduce the standby current.
The chip design is based on a 1T1MTJ MRAM cell with three metal layers: ground mesh, Write Word Line (WWL) and Bit Line (BL). Only three MRAM-specific levels (VA, MA, MTJ) are required beyond the three-Cu-level CMOS base technology. The low resistance ground mesh allows large uninterrupted arrays. The chip is divided into two 8Mbit units, each of which is split into 64 128Kbit blocks. Each 128Kbit block contains a single array and associated circuits.