16-bit processor core

Cambridge Consultants has released a new 16-bit RISC microprocessor IP core, which it will feature at the Design & Reuse IP-SoC conference in Grenoble, France on December 7th and 8th 2005.

The 16-bit XAP4 features a RISC architecture and is optimised for use in cost and performance sensitive ASIC designs. On a 0.18 micron CMOS fabrication process, the XAP4 can deliver up to 63 Dhrystone MIPS at a clock frequency of 117 MHz. This benchmark performance of 0.54 MIPS/MHz is a 50% improvement over Cambridge Consultants’ previous 16-bit processor, XAP2, which has been manufactured in hundreds of millions by licensees such as CSR, and in ZigBee radios, automotive devices and low-power industrial and medical sensors.

The XAP4 has both 16-bit data and address busses and is capable of running programs up to 64 kbytes. The first implementation of the processor has a two-stage pipelined Von Neumann architecture. It is delivered to licensees as a soft IP core in Verilog RTL that can be synthesised in as few as 12k gates for ASICs where die size and power consumption must be as small as possible. Cambridge Consultants has already delivered XAP4 to one licensee and is in discussion with other prospective customers at present.