Configurable SoC ICs

today revealed successful fabrication of the first of a family of configurable System-on-Chip ICs that addresses a variety of applications, including digital engines for printers, scanners and other embedded control applications.

Based upon ST's Structured Processor Enhanced Architecture (SPEAr), the device reportedly integrates an ARM core with a full set of IP (intellectual property) blocks and a configurable logic block that allows very fast customisation of critical functions in a fraction of the time and at a fraction of the cost required by a full custom design approach, but with a comparable level of flexibility and performance.

The family is based on industry-standard ARM cores that maximise the reuse of existing hardware and software blocks. The architecture includes a number of proven IPs for connectivity, memory interfaces, and a high-performance internal bus system.

Finally, a customisable embedded-logic block allows quick development of optimised solutions for specific markets by allowing customers to add their own proprietary IP to an ASSP (application-specific standard product) without embarking on a full ASIC design.