Designing microchip memories

As transistors on silicon chips get smaller, so tiny variations within their structures affect their performance and thus the reliability of the whole microchip. It is a problem that presents a huge barrier to the continued scaling of microchips and the development of ever more powerful computers.

To overcome this obstacle, the European Commission (EC) has established a taskforce to come up with ways of designing future microchip memories that take into account the variability and unreliability of nano-scale transistors.

The ’Tera-scale Reliable Adaptive Memory Systems’ (TRAMS) consortium includes Intel Iberia, Interuniversitair Micro-Elektronica Centrium, Glasgow University and the Universitat Politecnica de Catalunya, and is financed through the EU’s Framework Programme 7 (FP7) science-research fund.

Prof Asen Asenov of the Department of Electronic and Electrical Engineering is leading Glasgow University’s involvement in the project.

’If we are to continue to shrink the size of transistors in order to develop powerful circuits, we need fundamentally new approaches to circuit and system design that can take account of the variability within transistors. We hope this project will result in new chip-design paradigms for building reliable memory systems out of unreliable nano-scale components cheaply and effectively.’