According to Caltech, the new design – developed with researchers at Southampton University - could influence the future of data centres that manage very high volumes of data communication.
"Every time you are on a video call, stream a movie, or play an online video game, you're routing data back and forth through a data centre to be processed," said Caltech graduate student Arian Hashemi Talkhooncheh, lead author of a paper describing the two-chip innovation in the IEEE Journal of Solid-State Circuits. “There are more than 2,700 data centres in the US and more than 8,000 worldwide, with towers of servers stacked on top of each other to manage the load of thousands of terabytes of data going in and out every second."
The towers of servers in data centres heat up as they work, and some facilities have been built underwater to cool them more easily. The more efficient they can be made, the less heat they will generate and the greater the volume of information they will be able to manage.
Data processing is done on electronic circuits, while data transmission is done most efficiently using photonics. Achieving ultrahigh speed in each domain is challenging, but engineering the interface between them is even more difficult, Caltech said.
"There is a continuous demand for increasing the speed of data communication between different chips not only in data centres but also in high-performance computers. As the computing power of the chips scale, the communication speed can become the bottleneck, especially under stringent energy constraints," said Azita Emami, the Andrew and Peggy Cherng Professor of Electrical Engineering and Medical Engineering; executive officer for electrical engineering; and senior author of the paper.
To address this challenge, the Caltech/Southampton team designed an electronics chip and a photonics chip from the ground up and co-optimised them to work together. The process took four years to complete, with every design choice impacting both chips.
"We had to optimise the entire system all at the same time, which enabled achieving a superior power efficiency," Hashemi said in a statement. "These two chips are literally made for each other, integrated into one another in three dimensions."
The resulting optimised interface between the two chips allows them to transmit 100 gigabits of data per second while producing 2.4 pico-Joules per transmitted bit. This improves the electro-optical power efficiency of the transmission by a factor of 3.6 compared to the current state-of-the-art.
"As the world becomes more and more connected, and every device generates more data, it is exciting to show that we can achieve such high data rates while burning a fraction of power compared to the traditional techniques," said Emami.