New chip tech offers energy efficiency for AI devices

A new class of silicon systems that promise to enhance the energy efficiency of AI connected devices have been demonstrated in Singapore.

Professor Massimo Alioto, director of the FD-fAbrICS joint lab, speaking to participants from the industry and research community to share the latest developments in FD-SOI technologies at an industry showcase held on 3 May 2024
Professor Massimo Alioto, director of the FD-fAbrICS joint lab, speaking to participants from the industry and research community to share the latest developments in FD-SOI technologies at an industry showcase held on 3 May 2024 - NUS

The demonstrations were carried out by researchers from the National University of Singapore (NUS) and industry partners Soitec and NXP Semiconductors

The innovation has been demonstrated in fully-depleted silicon-on-insulator (FD-SOI) technology, and can be applied to the design and fabrication of advanced semiconductor components for AI applications.

According to NUS, the new chip technology has the potential to extend the battery life of wearables and smart objects by a factor of 10, support intense computational workloads for use in Internet of Things applications, and halve the power consumption associated with wireless communications with the cloud.

The new suite of chip technologies will be promoted through the FD-SOI & IoT Industry Consortium to accelerate industry adoption by lowering the design barrier to entry in FD-SOI chips.

An industry workshop titled 'Next-gen energy-efficient FD-SOI systems' was held on May 3, 2024 for participants from the industry and research community to share and discuss the latest developments in FD-SOI technologies, and showcase the new capabilities with demonstrations.

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