Meet Jeff Kodosky

2 min read

While National Instruments LabVIEW graphical programming language can help designers develop software for embedded systems, the company’s CompactRIO hardware plays an equally important role in helping them to deploy that software in a plethora of real-time environments.

The neat thing about the CompactRIO reconfigurable embedded system is that it not only sports a real-time embedded processor, but a four- or eight-slot chassis that contains a user-programmable Field Programmable Gate Array (FPGA) as well as hot-swappable industrial I/O modules.

That means that by using the LabVIEW dataflow programming language, designers can partition the software that they write for the hardware – real-time code can be targeted at the embedded processor, while time-critical functions can be used to synthesise the on-board logic of the FPGA, which can obviously run software a whole lot faster.

In the future, however, the distinction between the architecture of the embedded processor and the FPGA found in such systems will not be all that dissimilar. As the cores in general-purpose processors increase further in number, and their interconnection fabric becomes more complex, their hardware architectures may eventually converge with those found on future versions of FPGAs.

That, at least, is the opinion of Jeff Kodosky, the man who not only co-founded National Instruments, but who was the chief architect behind the LabVIEW graphical programming language.

He points to the fact that even today, the traditional sea of gates in the FPGA is already being complemented by groups of more highly specialised integrated functional blocks, and in the future he believes that both FPGAs and general-purpose embedded processors will sport a sea of interconnectivity, logic, memory and computational resources.

And, he adds, as the FPGAs increase in gate size and functionality and are deployed in cohorts with multi-core processors in future versions of National Instruments hardware, they will bring a new set of advantages to designers. Kodosky imagines a future where design engineers won’t need to partition the software for systems such as CompactRIO early on during the design cycle; instead the FPGAs would be partially reconfigurable – time-critical programs would be swapped in and out of the FPGA on-the-fly in a single-clock-cycle data-driven run-time environment.

Such architectures would inevitably demand that the software used to program the systems based upon them would need to be very different to the traditional programming languages such as C that are used today.

But Kodosky believes that here his company will have a distinct advantage due to the fact that the LabVIEW programming environment already allows designers to represent software parallelism as well as graphically exploit it through its case structure – the LabVIEW equivalent to the switch statements or if…then…else statements in text-based programming languages. As such, he believes that the programming environment is already perfectly positioned to take advantage of next generations of highly integrated CPUs and FPGA hardware.

After that, it’s anyone’s guess what software developments might be in the works. Perhaps one day, Mr Kodosky will figure out a way to let the LabVIEW software do all the work for the designer, inherently discovering the parallelism in the LabVIEW code and then matching it to models of the target hardware prior to any hardware development. It’s a vision of the future that doesn’t seem too far off.

Dave Wilson
Editor, Electronicstalk

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