Engineers in the US have fabricated transistors with 20nm gates — a development that could lead to faster, more compact and more efficient integrated circuits.
‘It’s a preview of things to come in the semiconductor industry,’ said Peide ‘Peter’ Ye, a professor of electrical and computer engineering at Purdue University.
Researchers from Purdue and Harvard universities created the transistors with indium-gallium-arsenide, a material that could replace silicon within a decade. Each transistor contains three tiny nanowires made from the material that are progressively smaller, yielding a tapered cross section that resembles a Christmas tree.
The research is said to build on previous work in which the team created a 3D structure instead of conventional flat transistors. It is claimed that the approach could enable engineers to build faster, more compact and more efficient integrated circuits and lighter laptops that generate less heat than those currently produced.
New findings show how to improve the device performance by linking the transistors vertically in parallel.
‘A one-storey house can hold so many people, but more floors, more people, and it’s the same thing with transistors,’ Ye said in a statement. ‘Stacking them results in more current and much faster operation for high-speed computing. This adds a whole new dimension, so I call them 4D.’
The latest silicon computer chips contain transistors with vertical 3D structures instead of conventional flat designs.
However, because silicon has a limited electron mobility, other materials are likely to be needed to continue advancing transistors with this 3D approach, Ye said.
Transistors contain gates, which enable the devices to switch on and off and to direct the flow of electrical current. Smaller gates make faster operation possible, and in current 3D silicon transistors the length of these gates is about 22nm.
The 3D design is critical because gate lengths of 22nm and smaller do not work well in a flat transistor architecture. Engineers are working to develop transistors that use smaller gate lengths; 14nm lengths are expected by 2015 and 10nm by 2018.
However, size reductions beyond 10nm and additional performance improvements are not likely to be possible using silicon, meaning new materials will be needed to continue progress, Ye said.
Creating smaller transistors will also require finding a new type of insulating, or dielectric, layer that allows the gate to switch off. As gate lengths shrink smaller than 14nm, the dielectric used in conventional transistors fails to perform properly and is said to lose electrical charge when the transistor is turned off.
Nanowires in the new transistors are coated with a different type of composite insulator, a 4nm-thick layer of lanthanum aluminate with an ultra-thin, half-nanometre layer of aluminium oxide.
The new ultra-thin dielectric allowed researchers to create transistors made of indium-gallium-arsenide with 20nm gates, which is a milestone, according to Ye.
Findings will be detailed in two papers to be presented during the International Electron Devices Meeting on 8–12 December in San Francisco.
The work is led by Purdue doctoral student Jiangjiang Gu and Harvard postdoctoral researcher Xinwei Wang.