The aim of the JDP is to produce a Complementary Metal Oxide Semiconductor, known as CMOS, with an initial accuracy of 90 nanometres (nm), which will be refined to an increased accuracy level of 65nm. A 110nm derivative will also be developed at the same time.
‘Our 90nm platform is a great starting point to build on because it is proven and will help shorten development cycle times significantly,’ said Prof Gilbert Declerck, president and CEO of IMEC.
The new technology will use a non-conductor insulator that stores a low level of electricity, known as a low-K intermetal dielectric, and a 193nm patterning process. These are two factors that are said to enable the creation of smaller die sizes and faster transistors.
The new CMOS will be ready for production by the end of 2008, where it is planned for use in communications and computers, as well as for a wide range of consumer products.