Toshiba has developed a new 3D memory array structure that relies on a novel method of stacking to enhance data capacity without relying on advances in process technology.
The design is a potential candidate technology for meeting future demand for higher density NAND flash memory.
Existing memory stacking technologies simply stack two-dimensional memory arrays on top of one another. While this achieves increased memory cell density, it makes the manufacturing process longer and more complex.
Toshiba’s new approach is based on increasing density without increasing a chip’s dimensions, as the number of connected elements increases in direct proportion to stack height.
To build the new device, the company first drives a through-hole down through a multi-layer sandwich of gate electrodes and insulator films. Pillars of silicon lightly doped with impurities are then deposited to fill in the holes. The gate electrode wraps around the silicon pillar at even intervals, and a pre-formed nitride film, for data-retention, set in each joint, functions as a NAND cell.
Toshiba plans to develop the technology further to the point where it can compete with current technology in terms of reliability.