A new processor architecture for high-definition (HD) video encoding has been announced by Santa Clara, CA-based Telairity Semiconductor.
Harnessing multiple independent vector/scalar cores, the multicore Telairity-1 architecture is specifically designed to handle the demanding computational requirements of the H.264 (MPEG-4 Part 10) HD codec.
H.264 is set to supersede MPEG-2 as the standard by which HD video is compressed in the professional broadcast environment for transmission, storage, and editing, where the new standard will deliver the same or better picture quality with a lower bit rate.
But a very powerful processor is required to implement the H.264 algorithm. An H.264 compression engine requires 4 to 6 times the computational power of an MPEG-2 compression engine.
The programmable Telairity-1 architecture delivers this power by combining five independent vector/scalar cores, a video controller, and a DRAM controller supporting an I/O bandwidth up to 5.3 Gbps in a single multicore SoC.
Each vector/scalar core features four vector pipes with independent hardware, an independent scalar unit, 128 Kbytes of on-chip vector SRAM, a 4 Kbyte vector SRAM data cache, an 8 Kbyte scalar scratchpad memory, and a 32-Kbyte instruction cache. As a fully programmable chip, Telairity-1 will allow customers to modify or add new algorithms to customize or improve the encoder over time.
At a clock rate of 668.25 MHz, or nine times the 74.25-MHz 20-bit video standard, the T1P2000, the first product implemented on the new architecture, achieves a total sustained chip performance of 55.5 GOP (Giga operations) per second.
Where a general-purpose, 600-MHz to 1-GHz DSP based real-time H.264 encoder implementation would require 18 to 32 DSPs and 6 or more FPGAs, the Telairity solution requires only four to eight Telairity video processor chips and one small FPGA to achieve equivalent bit rates.
Devices built on this architecture can be used for many different video encoding applications, allowing OEMs to use the same platform to deliver a range of capabilities. Beyond professional broadcast applications, the Telairity-1 processor will be used to enable HD video applications in video conferencing, security and surveillance, and medical imaging systems.
Packaged in the 1156-pin FCBGA (flip chip ball grid array) package, samples of the T1P2000 are available now, with production quantities available in Q4 2005. Pricing in 10,000-piece quantities for US delivery will start at $425.