ASIC prototyping

In support of the rapidly growing ASIC prototyping market, Synplicity has expanded its FPGA-based ASIC prototyping solution offerings by introducing Synplify Proto Single-Chip ASIC RTL Prototyping software.

The Synplify Proto software is claimed to be the first prototyping tool to address the need for single FPGA prototyping by integrating logic synthesis (Synplicity’s Synplify Pro Advanced FPGA synthesis) with debugging capabilities (Synplicity’s Identify RTL Debugger).

The product also includes a utility to convert instantiated Synopsys DesignWare IP in the customer’s ASIC RTL code to synthesizeable RTL equivalents for the FPGA.

Synplicity used its prototyping expertise to develop the Synplify Proto software and to provide customers who prototype using a single FPGA with similar performance benefits as its multi-FPGA solution, Certify ASIC RTL Prototyping software.

Features of both prototyping tools include automatic recognition and translation of ASIC elements, such as gate-level components or gated-clock tree structures, to an appropriate form for FPGA implementation.