Sixty four cores

Tilera Corporation has launched its TILE64 processor, the first in a family of Tile Processor chips based on an architecture that, it claims, can scale to hundreds and even thousands of cores.

The TILE64 processor contains 64 full-featured, programmable cores - each capable of running Linux. Initial target markets for the processor include the embedded networking and digital multimedia markets.

Tilera was founded to bring to market the MIT research of Dr. Anant Agarwal who first created the mesh-based multicore architecture in 1996. The "Raw" project received multi-million dollar DARPA and National Science Foundation grants and spawned the development of the first tiled multicore processor prototype and associated multicore software in 2002.

The company has a dozen customers who are currently integrating the TILE64 processor into products for advanced networking and digital multimedia applications.

Tilera's new architecture eliminates the on-chip bus interconnect, a kind of centralized intersection that information must flow through between cores within a chip, or before it leaves the chip. As engineers have added more cores to chips, the bus has created an information traffic jam because packets from these cores all must travel to one central point, like a spoke-and-wheel traffic intersection in an old city.