Video encoder

A new processor architecture for high-definition (HD) video encoding has been announced by Santa Clara, CA-based Telairity Semiconductor.

Harnessing multiple independent vector/scalar cores, the multicore Telairity-1 architecture is specifically designed to handle the demanding computational requirements of the H.264 (MPEG-4 Part 10) HD codec.

H.264 is set to supersede MPEG-2 as the standard by which HD video is compressed in the professional broadcast environment for transmission, storage, and editing, where the new standard will deliver the same or better picture quality with a lower bit rate.

But a very powerful processor is required to implement the H.264 algorithm. An H.264 compression engine requires 4 to 6 times the computational power of an MPEG-2 compression engine.

The programmable Telairity-1 architecture delivers this power by combining five independent vector/scalar cores, a video controller, and a DRAM controller supporting an I/O bandwidth up to 5.3 Gbps in a single multicore SoC.